Summary: | missed optimization in switch of modulus value | ||
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Product: | gcc | Reporter: | Ulrich Drepper <drepper.fsp+rhbz> |
Component: | middle-end | Assignee: | Not yet assigned to anyone <unassigned> |
Status: | NEW --- | ||
Severity: | enhancement | CC: | tulipawn |
Priority: | P3 | Keywords: | missed-optimization |
Version: | 7.0 | ||
Target Milestone: | --- | ||
Host: | Target: | ||
Build: | Known to work: | ||
Known to fail: | Last reconfirmed: | 2016-10-06 00:00:00 |
Description
Ulrich Drepper
2016-10-06 00:14:52 UTC
The point is that with the modulus visible VRP will remove the default case (or rather take a random one -- here the first one -- as new default): <bb 2>: n_9 = n_8(D) % 3; switch (n_9) <default: <L0>, case 1: <L1>, case 2: <L2>> <L0>: zero.0_1 = zero; _2 = zero.0_1 + 1; zero = _2; goto <bb 6>; <L1>: one.1_3 = one; _4 = one.1_3 + 1; one = _4; goto <bb 6>; <L2>: two.2_5 = two; _6 = two.2_5 + 1; two = _6; <bb 6>: return; if we don't have the modulo then the default case will not be optimized away (not the one with the unreachable either) before RTL expansion. So it looks like the four-cases variant where one case later vanishes happens to be expanded better. Which means we should improve expansion for the IL case above (stmt.c:expand_case). Or work around by choosing another value as the "default" if that makes expand_case happy. |