Summary: | [SH] Group T bit related insns before combine | ||
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Product: | gcc | Reporter: | Oleg Endo <olegendo> |
Component: | target | Assignee: | Not yet assigned to anyone <unassigned> |
Status: | NEW --- | ||
Severity: | enhancement | CC: | pietro.gcc |
Priority: | P3 | ||
Version: | 4.9.0 | ||
Target Milestone: | --- | ||
Host: | Target: | sh*-*-* | |
Build: | Known to work: | ||
Known to fail: | Last reconfirmed: | 2024-05-27 00:00:00 |
Description
Oleg Endo
2013-11-25 17:42:03 UTC
Is this still valid? GCC 14 on the Compiler Explorer[0] show GCC 9.5 producing the same assembly, but 12 and above (it doesn't have SH GCC 10 and 11) produces: _test2: cmp/eq r5,r4 mov r5,r1 add r6,r1 add #1,r1 rts movt r0 [0]: https://godbolt.org/z/668ax5ehj (In reply to pietro from comment #1) > Is this still valid? GCC 14 on the Compiler Explorer[0] show GCC 9.5 > producing the same assembly, but 12 and above (it doesn't have SH GCC 10 and > 11) produces: > > _test2: > cmp/eq r5,r4 > mov r5,r1 > add r6,r1 > add #1,r1 > rts > movt r0 > > [0]: https://godbolt.org/z/668ax5ehj Yes, still valid. Nothing has been done to explicitly address or improve the issue. The ideal code should be something like: cmp/eq r5,r4 movt r0 sett addc r5,r6 rts mov r6,r1 The following peehole: (define_peephole [(set (match_operand:SI 0 "arith_reg_dest") (plus:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand"))) (set (match_operand:SI 2 "arith_reg_dest") (plus:SI (match_dup 2) (const_int 1)))] "TARGET_SH1 && REGNO (operands[0]) == REGNO (operands[2])" { return "sett" "\n" "\taddc %1,%0"; }) generates: cmp/eq r5,r4 mov r5,r1 sett addc r6,r1 rts movt r0 I tried this one too: (define_peephole2 [(set (match_operand:SI 0 "arith_reg_dest") (plus:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand"))) (set (match_operand:SI 2 "arith_reg_dest") (plus:SI (match_dup 2) (const_int 1)))] "TARGET_SH1 && REGNO (operands[0]) == REGNO (operands[2])" [(const_int 0)] { emit_insn (gen_sett ()); emit_insn (gen_addc (operands[0], operands[0], operands[1])); }) but then the cmp/eq is swallowed: sett mov r5,r1 addc r6,r1 rts movt r0 (In reply to pietro from comment #3) > The following peehole: > > (define_peephole > [(set (match_operand:SI 0 "arith_reg_dest") > (plus:SI (match_dup 0) > (match_operand:SI 1 "arith_reg_operand"))) > (set (match_operand:SI 2 "arith_reg_dest") > (plus:SI (match_dup 2) > (const_int 1)))] > "TARGET_SH1 > && REGNO (operands[0]) == REGNO (operands[2])" > { > return "sett" "\n" > "\taddc %1,%0"; > }) > The use of old style text based peepholes is not preferred in general. Other than that, reducing the live ranges of the T bit register (by grouping the related insns closer together) should be better done much earlier, before register allocation. (peephole pass is done way later in the optimization flow). |