| Summary: | GCC creates suboptimal ASM : suboptimal Adressing-Modes used | ||
|---|---|---|---|
| Product: | gcc | Reporter: | Gunnar von Boehn <gunnar> |
| Component: | target | Assignee: | Not yet assigned to anyone <unassigned> |
| Status: | RESOLVED DUPLICATE | ||
| Severity: | enhancement | CC: | aldot, alexandre.nunes, dje, ebotcazou, fang, gcc-bugs, gunnar, hp, krebbel, mark, pinskia, rakdver, schwab, stevenb.gcc, tbm |
| Priority: | P3 | Keywords: | missed-optimization |
| Version: | 4.2.1 | ||
| Target Milestone: | --- | ||
| Host: | i686-pc-linux-gnu | Target: | m68k-linux-gnu |
| Build: | i686-pc-linux-gnu | Known to work: | |
| Known to fail: | Last reconfirmed: | ||
|
Description
Gunnar von Boehn
2008-05-05 13:54:39 UTC
It would have been nice to check at least gcc 4.3 (or better current trunk). (In reply to comment #1) > It would have been nice to check at least gcc 4.3 (or better current trunk). > I have verified this for you with the most current GCC source. Verified with gcc version 4.4.0 20080523 (experimental) (GCC) The problem that GCC uses bad addressing modes is still persistent. Code generated by GCC 4.4 copy_32x4: link.w %fp,#-12 movem.l #3076,(%sp) move.l 16(%fp),%d2 lsr.l #4,%d2 move.l 8(%fp),%a3 move.l 12(%fp),%a2 jra .L6 .L7: move.l (%a2),%a1 subq.l #1,%d2 move.l 4(%a2),%d0 move.l 8(%a2),%d1 move.l 12(%a2),%a0 add.l #16,%a2 move.l %a1,(%a3) move.l %d0,4(%a3) move.l %d1,8(%a3) move.l %a0,12(%a3) add.l #16,%a3 .L6: tst.l %d2 jne .L7 movem.l (%sp),#3076 unlk %fp rts Andreas,
What is your opinion to this?
GCC 2.9 used to combine the move with increment in the combine step to something like this:
***
(insn 32 30 33 (set (reg/v:SI 32)
(mem:SI (post_inc:SI (reg/v:SI 34)) 0)) 42 {movsi+1} (nil)
(expr_list:REG_INC (reg/v:SI 34)
(nil)))
***
So problem is that now GCC seems not to be able to do this anymore by itself
With GCC 4.4 the output is:
**
(insn 34 33 35 4 example2.c:11 (set (reg/v:SI 54 [ value ])
(mem:SI (reg/v/f:SI 52 [ src ]) [2 S4 A16])) 37 {*movsi_cf} (nil))
(insn 35 34 36 4 example2.c:12 (set (reg/v:SI 53 [ value2 ])
(mem:SI (plus:SI (reg/v/f:SI 52 [ src ])
(const_int 4 [0x4])) [2 S4 A16])) 37 {*movsi_cf} (nil))
(insn 36 35 38 4 example2.c:5 (set (reg/v/f:SI 52 [ src ])
(plus:SI (reg/v/f:SI 52 [ src ])
(const_int 8 [0x8]))) 133 {*addsi3_5200} (nil))
(insn 38 36 40 4 example2.c:10 (set (reg/v:SI 50 [ size.21 ])
(plus:SI (reg/v:SI 50 [ size.21 ])
(const_int -1 [0xffffffff]))) 133 {*addsi3_5200} (nil))
***
Any ideas about this?
Kind regards
Gunnar von Boehn
This comes down to IV-OPTs not understanding {post,pre}_{dec,inc} at all. There is another bug about this somewhere I think for arm. PowerPC has the same issue too ...
(In reply to comment #4) > This comes down to IV-OPTs not understanding {post,pre}_{dec,inc} at all. > There is another bug about this somewhere I think for arm. PowerPC has the > same issue too ... > If this effects so many platforms this sounds like an important issue to me. Maybe someone should increase the priority and severity of the issue in this case? Andrew, do you plan to fix this issue? Cheers Gunnar (In reply to comment #4) > This comes down to IV-OPTs not understanding {post,pre}_{dec,inc} at all. > There is another bug about this somewhere I think for arm. PowerPC has the > same issue too ... > Hi Andrew, I want to make clear that the 68K backend used to be able to do this optimization in the GCC 2.9 times. Later with 3.4 or 4.x this optmization did not work anymore and the code became worth. Does this make sense in your opinion? Cheers |