Bug 33413

For most ARM architecture variants, the only atomic operation is swap.  The semantics of the SWP instruction are what gcc calls __sync_lock_test_and_set (a rather odd name since the set is unconditional).  Would it be possible to add a __sync_lock_test_and_set builtin for ARM that generates a SWP instruction?

It would be useful to also provide a predefined macro that can be tested to determine whether the builtin is implemented.  Typically, code that wants to do architecture-independent atomic operations will want to do something like:

#if have atomic add etc
... atomic operations using those builtins
#elsif have atomic swap
... atomic operations using swap
#else
... atomic operations using pthreads, or #error
#end

I understand that __GCC_HAVE_SYNC_COMPARE_AND_SWAP_n can be tested for the first #if above (on sufficiently new compilers), on the basis that an architecture that provides compare-and-swap can use it to synthesize all of the other builtin atomic operations.  However, swap is not sufficient to implement the other builtins without some additional constraints, e.g. a sentinel value, and assumptions about the threading model.

For discussions please see:
http://thread.gmane.org/gmane.comp.gcc.help/21113

Thanks,  Phil.