Summary: | [4.0 Regression] ICE with -march=pentium-m (during bootstrap) | ||
---|---|---|---|
Product: | gcc | Reporter: | arend.bayer <arend.bayer> |
Component: | target | Assignee: | Richard Henderson <rth> |
Status: | RESOLVED FIXED | ||
Severity: | normal | CC: | gcc-bugs, rth |
Priority: | P2 | Keywords: | build, ice-on-valid-code, ssemmx |
Version: | 4.0.0 | ||
Target Milestone: | 4.0.0 | ||
Host: | i686-pc-linux-gnu | Target: | |
Build: | Known to work: | ||
Known to fail: | Last reconfirmed: | 2005-01-24 01:11:52 | |
Attachments: | preprocessed source |
Description
arend.bayer@web.de
2005-01-21 00:30:13 UTC
Created attachment 8025 [details]
preprocessed source
This is as reduced as I can get it (80 lines): typedef unsigned int size_t; extern void __assert_fail () __attribute__ ((__noreturn__)); typedef unsigned int uintptr_t; extern int __mf_heuristic_check (uintptr_t, uintptr_t); struct __mf_options { unsigned adapt_cache; enum { mode_nop, mode_check } mudflap_mode; }; extern enum __mf_state_enum __mf_state; extern int __mf_starting_p; extern struct __mf_options __mf_opts; typedef struct __mf_object { unsigned read_count, write_count, liveness; } __mf_object_t; unsigned __mf_find_objects (uintptr_t ptr_low, uintptr_t ptr_high, __mf_object_t **objs, unsigned max_objs); void __mf_adapt_cache (void); void __mfu_check (void *ptr, size_t sz, int type) { int judgement = 0; uintptr_t ptr_low = (uintptr_t) ptr; uintptr_t ptr_high = (sz ? (((uintptr_t) ptr) <= (~ (uintptr_t) 0)-(sz)+1 ? ((uintptr_t) ptr)+((uintptr_t) sz) - 1 : (~ (uintptr_t) 0)) : ((uintptr_t) ptr)); switch (__mf_opts.mudflap_mode) { case mode_nop: break; case mode_check: { unsigned heuristics = 0; static unsigned adapt_count; adapt_count ++; if ((__builtin_expect (!!(__mf_opts.adapt_cache > 0 && adapt_count > __mf_opts.adapt_cache), 0))) { adapt_count = 0; __mf_adapt_cache (); } while (judgement == 0) { extern void __real_free (void *p); __mf_object_t* ovr_obj[1]; unsigned obj_count; __mf_object_t** all_ovr_obj = ((void *)0); __mf_object_t** dealloc_me = ((void *)0); unsigned i; obj_count = __mf_find_objects (ptr_low, ptr_high, ovr_obj, 1); if ((__builtin_expect (!!(obj_count > 1), 0))) { extern void * __real_malloc (size_t c); unsigned n; all_ovr_obj = __real_malloc ((sizeof (__mf_object_t *) * obj_count)); n = __mf_find_objects (ptr_low, ptr_high, all_ovr_obj, obj_count); ((void) (__builtin_expect (!!(n == obj_count), 1) ? 0 : (__assert_fail (), 0))); dealloc_me = all_ovr_obj; } else { all_ovr_obj = ovr_obj; dealloc_me = ((void *)0); } for (i = 0; i < obj_count; i++) { __mf_object_t *obj = all_ovr_obj[i]; ((void) (__builtin_expect (!!(obj != ((void *)0)), 1) ? 0 : (__assert_fail (), 0))); if (type == 0) obj->read_count ++; } if (dealloc_me != ((void *)0)) __real_free (dealloc_me); if (heuristics++ < 2) judgement = __mf_heuristic_check (ptr_low, ptr_high); } } } } Looks like a reload problem (of course). In the .lreg dump we have this: (insn:HI 100 99 101 9 (set (reg/v/f:SI 64 [ all_ovr_obj ]) (reg/f:SI 87)) 41 {*movsi_1} (nil) (nil)) In the .greg dump we get these reloads for insn 100: Spilling for insn 100. ... Spilling for insn 100. ... Reloads for insn # 100 Reload 0: reload_in (SI) = (plus:SI (reg/f:SI 6 bp) (const_int -28 [0xffffffffffffffe4])) SSE_REGS, RELOAD_FOR_INPUT (opnum = 1) reload_in_reg: (plus:SI (reg/f:SI 6 bp) (const_int -28 [0xffffffffffffffe4])) reload_reg_rtx: (reg/v/f:SI 21 xmm0 [orig:64 all_ovr_obj ] [64]) ... At the moment of the ICE we have this: (insn 287 99 288 8 (set (reg/v/f:SI 21 xmm0 [orig:64 all_ovr_obj ] [64]) (reg/f:SI 6 bp)) 41 {*movsi_1} (nil) (nil)) (insn 288 287 100 8 (set (reg/v/f:SI 21 xmm0 [orig:64 all_ovr_obj ] [64]) (plus:SI (reg/v/f:SI 21 xmm0 [orig:64 all_ovr_obj ] [64]) (const_int -28 [0xffffffffffffffe4]))) -1 (nil) (expr_list:REG_EQUIV (plus:SI (reg/f:SI 6 bp) (const_int -28 [0xffffffffffffffe4])) (nil))) (insn:HI 100 288 101 8 (set (reg/v/f:SI 21 xmm0 [orig:64 all_ovr_obj ] [64]) (reg/v/f:SI 21 xmm0 [orig:64 all_ovr_obj ] [64])) 41 {*movsi_1} (nil) (nil)) Why does reload reload an SImode register to an sse register? Subject: Re: [4.0 Regression] ICE with -march=pentium-m (during bootstrap) I verified it still ICEs as of today (2005-01-21). Subject: Bug 19556 CVSROOT: /cvs/gcc Module name: gcc Changes by: rth@gcc.gnu.org 2005-01-25 18:44:05 Modified files: gcc : ChangeLog gcc/config/i386: i386.c i386.md Log message: PR target/19556 PR target/19584 * config/i386/i386.c (x86_inter_unit_moves): Zero. (ix86_preferred_reload_class): Rewrite fp-constant section, with 80387 enabled, to return a proper subclass. Return the subset that overlaps with GENERAL_REGS for PLUS. * config/i386/i386.md (movsi_1, movdi_2): Set type to "mmx" for pxor. Patches: http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/ChangeLog.diff?cvsroot=gcc&r1=2.7270&r2=2.7271 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/i386/i386.c.diff?cvsroot=gcc&r1=1.789&r2=1.790 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/i386/i386.md.diff?cvsroot=gcc&r1=1.612&r2=1.613 |