| Summary: | [3.4/4.0 Regression] ICE with mode attribute on structures | ||
|---|---|---|---|
| Product: | gcc | Reporter: | Pawel Sikora <pawel_sikora> |
| Component: | c | Assignee: | Richard Henderson <rth> |
| Status: | RESOLVED FIXED | ||
| Severity: | normal | CC: | gcc-bugs |
| Priority: | P2 | ||
| Version: | 3.4.2 | ||
| Target Milestone: | 3.4.3 | ||
| Host: | pentium3-pld-linux | Target: | arm-pld-linux |
| Build: | pentium3-pld-linux | Known to work: | |
| Known to fail: | Last reconfirmed: | 2004-09-09 21:07:39 | |
: Search converges between 2003-08-30-trunk (#339) and 2003-09-02-trunk (#340). input.c:9: internal compiler error: tree check: expected tree_list, have integer_cst in finish_struct, at c- decl.c:5150 Please submit a full bug report, with preprocessed source if appropriate. See for instructions. Confirmed. Working on a fix for the ICE, but I'll warn you that this construct is erroneous. You don't get to choose the mode for a structure; that's determined by the layout routines. As for your hardware registers, no there's no way to do this with a structure. You'll need to explicitly read these registers with an integer type. You might look into the transparent union extension that would let you cast between integer and structure types. Subject: Bug 17384 CVSROOT: /cvs/gcc Module name: gcc Branch: gcc-3_4-branch Changes by: rth@gcc.gnu.org 2004-10-13 23:29:06 Modified files: gcc : ChangeLog c-common.c crtstuff.c gcc/config/i386: emmintrin.h xmmintrin.h Log message: PR c/17384 * c-common.c (handle_mode_attribute): Disallow mode changes that alter the CODE of the top-level type. * crtstuff.c (__FRAME_END__): Remove mode attribute. Find 32-bit integer from internal limits macros. * config/i386/emmintrin.h (__v2df): Fix base type. * config/i386/xmmintrin.h (__m128, __v4sf): Likewise. Patches: http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/ChangeLog.diff?cvsroot=gcc&only_with_tag=gcc-3_4-branch&r1=2.2326.2.656&r2=2.2326.2.657 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/c-common.c.diff?cvsroot=gcc&only_with_tag=gcc-3_4-branch&r1=1.476.4.8&r2=1.476.4.9 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/crtstuff.c.diff?cvsroot=gcc&only_with_tag=gcc-3_4-branch&r1=1.65&r2=1.65.4.1 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/i386/emmintrin.h.diff?cvsroot=gcc&only_with_tag=gcc-3_4-branch&r1=1.4.4.1&r2=1.4.4.2 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/i386/xmmintrin.h.diff?cvsroot=gcc&only_with_tag=gcc-3_4-branch&r1=1.27.4.1&r2=1.27.4.2 Subject: Bug 17384 CVSROOT: /cvs/gcc Module name: gcc Changes by: rth@gcc.gnu.org 2004-10-13 23:31:24 Modified files: gcc : ChangeLog c-common.c crtstuff.c gcc/config/i386: mm3dnow.h Added files: gcc/testsuite/gcc.dg: attr-mode-1.c Log message: PR c/17384 * c-common.c (handle_mode_attribute): Disallow mode changes that alter the CODE of the top-level type. * crtstuff.c (__FRAME_END__): Remove mode attribute. Find 32-bit integer from internal limits macros. * config/i386/mm3dnow.h (__v2sf): Fix base type. Patches: http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/ChangeLog.diff?cvsroot=gcc&r1=2.5869&r2=2.5870 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/c-common.c.diff?cvsroot=gcc&r1=1.576&r2=1.577 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/crtstuff.c.diff?cvsroot=gcc&r1=1.68&r2=1.69 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/i386/mm3dnow.h.diff?cvsroot=gcc&r1=1.1&r2=1.2 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/testsuite/gcc.dg/attr-mode-1.c.diff?cvsroot=gcc&r1=NONE&r2=1.1 Fixed. |
# testcase # typedef struct __attribute__((mode(SI))) { unsigned INT0 :1, RES0 :1, :6, INT1 :1, RES1 :1, :6, :16; } MCR; # arm-pld-linux-gcc bitfields.c -c bitfields.c:9: internal compiler error: Segmentation fault ps). /bitfields-related/ Is there a possibility to turn off the unaligned access (via LDRB(H)/STRB(H)) to specified bitfields? Many of registers mapped into ARM7's address space don't work correctly with such kind of access. The problem is that gcc will generate 8/16/32 bits access for bit field access depending on the width of the bit field. This is allowed for memory based operations if the memeory accepts 8/16/32 bit transfers (most configurations do), but deadly in case of I/O registers that can only be written 32 bits at a time. Do You plan to introduce something like __attribute__((only_full_word_access)) ?