Attachment #9454 for bug #19653

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Lines 1231-1245 push_reload (rtx in, rtx out, rtx *inloc Link Here

(-)reload.c (-18 / +41 lines)
1231		1231
1232	/* Narrow down the class of register wanted if that is	1232	/* Narrow down the class of register wanted if that is
1233	desirable on this machine for efficiency. */	1233	desirable on this machine for efficiency. */
1234	if (in != 0)	1234	{
1235	class = PREFERRED_RELOAD_CLASS (in, class);	1235	enum reg_class preferred_class = class;
		1236
		1237	if (in != 0)
		1238	preferred_class = PREFERRED_RELOAD_CLASS (in, class);
1236		1239
1237	/* Output reloads may need analogous treatment, different in detail. */	1240	/* Output reloads may need analogous treatment, different in detail. */
1238	#ifdef PREFERRED_OUTPUT_RELOAD_CLASS	1241	#ifdef PREFERRED_OUTPUT_RELOAD_CLASS
1239	if (out != 0)	1242	if (out != 0)
1240	class = PREFERRED_OUTPUT_RELOAD_CLASS (out, class);	1243	preferred_class = PREFERRED_OUTPUT_RELOAD_CLASS (out, preferred_class);
1241	#endif	1244	#endif
1242		1245
		1246	/* Discard what the target said if we cannot do it. */
		1247	if (preferred_class != NO_REGS
		1248	\|\| (optional && type == RELOAD_FOR_OUTPUT))
		1249	class = preferred_class;
		1250	}
		1251
1243	/* Make sure we use a class that can handle the actual pseudo	1252	/* Make sure we use a class that can handle the actual pseudo
1244	inside any subreg. For example, on the 386, QImode regs	1253	inside any subreg. For example, on the 386, QImode regs
1245	can appear within SImode subregs. Although GENERAL_REGS	1254	can appear within SImode subregs. Although GENERAL_REGS
Lines 1937-1943 find_dummy_reload (rtx real_in, rtx real Link Here
1937		1946
1938	/* Narrow down the reg class, the same way push_reload will;	1947	/* Narrow down the reg class, the same way push_reload will;
1939	otherwise we might find a dummy now, but push_reload won't. */	1948	otherwise we might find a dummy now, but push_reload won't. */
1940	class = PREFERRED_RELOAD_CLASS (in, class);	1949	{
		1950	enum reg_class preferred_class = PREFERRED_RELOAD_CLASS (in, class);
		1951	if (class != NO_REGS)
		1952	class = preferred_class;
		1953	}
1941		1954
1942	/* See if OUT will do. */	1955	/* See if OUT will do. */
1943	if (REG_P (out)	1956	if (REG_P (out)
Lines 3451-3472 find_reloads (rtx insn, int replace, int Link Here
3451	losers++;	3464	losers++;
3452	}	3465	}
3453		3466
3454	/* If we can't reload this value at all, reject this
3455	alternative. Note that we could also lose due to
3456	LIMIT_RELOAD_RELOAD_CLASS, but we don't check that
3457	here. */
3458
3459	if (! CONSTANT_P (operand)
3460	&& (enum reg_class) this_alternative[i] != NO_REGS
3461	&& (PREFERRED_RELOAD_CLASS (operand,
3462	(enum reg_class) this_alternative[i])
3463	== NO_REGS))
3464	bad = 1;
3465
3466	/* Alternative loses if it requires a type of reload not	3467	/* Alternative loses if it requires a type of reload not
3467	permitted for this insn. We can always reload SCRATCH	3468	permitted for this insn. We can always reload SCRATCH
3468	and objects with a REG_UNUSED note. */	3469	and objects with a REG_UNUSED note. */
3469	else if (GET_CODE (operand) != SCRATCH	3470	if (GET_CODE (operand) != SCRATCH
3470	&& modified[i] != RELOAD_READ && no_output_reloads	3471	&& modified[i] != RELOAD_READ && no_output_reloads
3471	&& ! find_reg_note (insn, REG_UNUSED, operand))	3472	&& ! find_reg_note (insn, REG_UNUSED, operand))
3472	bad = 1;	3473	bad = 1;
Lines 3474-3479 find_reloads (rtx insn, int replace, int Link Here
3474	&& ! const_to_mem)	3475	&& ! const_to_mem)
3475	bad = 1;	3476	bad = 1;
3476		3477
		3478	/* If we can't reload this value at all, reject this
		3479	alternative. Note that we could also lose due to
		3480	LIMIT_RELOAD_CLASS, but we don't check that
		3481	here. */
		3482
		3483	if (! CONSTANT_P (operand)
		3484	&& (enum reg_class) this_alternative[i] != NO_REGS)
		3485	{
		3486	if (PREFERRED_RELOAD_CLASS
		3487	(operand, (enum reg_class) this_alternative[i])
		3488	== NO_REGS)
		3489	reject = 600;
		3490
		3491	#ifdef PREFERRED_OUTPUT_RELOAD_CLASS
		3492	if (operand_type[i] == RELOAD_FOR_OUTPUT
		3493	&& PREFERRED_OUTPUT_RELOAD_CLASS
		3494	(operand, (enum reg_class) this_alternative[i])
		3495	== NO_REGS)
		3496	reject = 600;
		3497	#endif
		3498	}
		3499
3477	/* We prefer to reload pseudos over reloading other things,	3500	/* We prefer to reload pseudos over reloading other things,
3478	since such reloads may be able to be eliminated later.	3501	since such reloads may be able to be eliminated later.
3479	If we are reloading a SCRATCH, we won't be generating any	3502	If we are reloading a SCRATCH, we won't be generating any

Lines 2385-2396 Link Here

(-)doc/tm.texi (+10 lines)
2385	into any kind of register, code generation will be better if	2385	into any kind of register, code generation will be better if
2386	@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead	2386	@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
2387	of using @code{PREFERRED_RELOAD_CLASS}.	2387	of using @code{PREFERRED_RELOAD_CLASS}.
		2388
		2389	If an insn has pseudos in it after register allocation, reload will go
		2390	through the alternatives and call repeatedly @code{PREFERRED_RELOAD_CLASS}
		2391	to find the best one. Returning @code{NO_REGS}, in this case, makes
		2392	reload add a @code{!} in front of the constraint: the x86 back-end uses
		2393	this feature to discourage usage of 387 registers when math is done in
		2394	the SSE registers (and vice versa).
2388	@end defmac	2395	@end defmac
2389		2396
2390	@defmac PREFERRED_OUTPUT_RELOAD_CLASS (@var{x}, @var{class})	2397	@defmac PREFERRED_OUTPUT_RELOAD_CLASS (@var{x}, @var{class})
2391	Like @code{PREFERRED_RELOAD_CLASS}, but for output reloads instead of	2398	Like @code{PREFERRED_RELOAD_CLASS}, but for output reloads instead of
2392	input reloads. If you don't define this macro, the default is to use	2399	input reloads. If you don't define this macro, the default is to use
2393	@var{class}, unchanged.	2400	@var{class}, unchanged.
		2401
		2402	You can also use @code{PREFERRED_OUTPUT_RELOAD_CLASS} to discourage
		2403	reload from using some alternatives, like @code{PREFERRED_RELOAD_CLASS}.
2394	@end defmac	2404	@end defmac
2395		2405
2396	@defmac LIMIT_RELOAD_CLASS (@var{mode}, @var{class})	2406	@defmac LIMIT_RELOAD_CLASS (@var{mode}, @var{class})




enum reg_class
ix86_preferred_reload_class (rtx x, enum reg_class class)
{
  enum machine_mode mode = GET_MODE (x);

  /* We're only allowed to return a subclass of CLASS.  Many of the 
     following checks fail for NO_REGS, so eliminate that early.  */
  if (class == NO_REGS)
    return NO_REGS;

  /* All classes can load zeros.  */
  if (x == CONST0_RTX (mode))
    return class;

  /* Force constants into memory if we are loading into MMX or SSE registers,
     because there are no MMX/SSE instructions to load from a constant.  */
  if (CONSTANT_P (x)
      && (MAYBE_MMX_CLASS_P (class) || MAYBE_SSE_CLASS_P (class)))
    return NO_REGS;

  /* Prefer SSE regs only, if we can use them for math.  */
  if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
    return SSE_CLASS_P (class) ? class : NO_REGS;

  /* Floating-point constants need more complex checks.  */
  if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
    {

	 zero above.  We only want to wind up preferring 80387 registers if
	 we plan on doing computation with them.  */
      if (TARGET_80387
	  && (TARGET_MIX_SSE_I387 
	      || !(TARGET_SSE_MATH && SSE_FLOAT_MODE_P (GET_MODE (x))))
	  && standard_80387_constant_p (x))
	{
	  /* Limit class to non-sse.  */


      return NO_REGS;
    }
  if (MAYBE_MMX_CLASS_P (class) && CONSTANT_P (x))
    return NO_REGS;
  if (MAYBE_SSE_CLASS_P (class) && CONSTANT_P (x))
    return NO_REGS;

  /* Generally when we see PLUS here, it's the function invariant
     (plus soft-fp const_int).  Which can only be computed into general

  return class;
}

/* Discourage putting floating-point values in SSE registers unless
   SSE math is being used, and likewise for the 387 registers.  */
enum reg_class
ix86_preferred_output_reload_class (rtx x, enum reg_class class)
{
  enum machine_mode mode = GET_MODE (x);

  /* Restrict the output reload class to the register bank that we are doing
     math on.  If we would like not to return a subset of CLASS, reject this
     alternative: if reload cannot do this, it will still use its choice.  */
  mode = GET_MODE (x);
  if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
    return MAYBE_SSE_CLASS_P (class) ? SSE_REGS : NO_REGS;

  if (TARGET_80387 && SCALAR_FLOAT_MODE_P (mode))
    {
      if (class == FP_TOP_SSE_REGS)
	return FP_TOP_REG;
      else if (class == FP_SECOND_SSE_REGS)
	return FP_SECOND_REG;
      else
	return FLOAT_CLASS_P (class) ? class : NO_REGS;
    }

  return class;
}

/* If we are copying between general and FP registers, we need a memory
   location. The same is true for SSE and MMX registers.


Lines 1294-1299 Link Here

(-)config/i386/i386.h (+6 lines)
1294	#define PREFERRED_RELOAD_CLASS(X, CLASS) \	1294	#define PREFERRED_RELOAD_CLASS(X, CLASS) \
1295	ix86_preferred_reload_class ((X), (CLASS))	1295	ix86_preferred_reload_class ((X), (CLASS))
1296		1296
		1297	/* Discourage putting floating-point values in SSE registers unless
		1298	SSE math is being used, and likewise for the 387 registers. */
		1299
		1300	#define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
		1301	ix86_preferred_output_reload_class ((X), (CLASS))
		1302
1297	/* If we are copying between general and FP registers, we need a memory	1303	/* If we are copying between general and FP registers, we need a memory
1298	location. The same is true for SSE and MMX registers. */	1304	location. The same is true for SSE and MMX registers. */
1299	#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \	1305	#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \

Lines 188-193 Link Here

(-)config/i386/i386-protos.h (+1 lines)
188	extern bool ix86_cannot_change_mode_class (enum machine_mode,	188	extern bool ix86_cannot_change_mode_class (enum machine_mode,
189	enum machine_mode, enum reg_class);	189	enum machine_mode, enum reg_class);
190	extern enum reg_class ix86_preferred_reload_class (rtx, enum reg_class);	190	extern enum reg_class ix86_preferred_reload_class (rtx, enum reg_class);
		191	extern enum reg_class ix86_preferred_output_reload_class (rtx, enum reg_class);
191	extern int ix86_memory_move_cost (enum machine_mode, enum reg_class, int);	192	extern int ix86_memory_move_cost (enum machine_mode, enum reg_class, int);
192	extern int ix86_mode_needed (int, rtx);	193	extern int ix86_mode_needed (int, rtx);
193	extern void emit_i387_cw_initialization (int);	194	extern void emit_i387_cw_initialization (int);





(define_insn "*cmpfp_i_mixed"
  [(set (reg:CCFP FLAGS_REG)
	(compare:CCFP (match_operand 0 "register_operand" "f,x")
		      (match_operand 1 "nonimmediate_operand" "f,xm")))]
  "TARGET_MIX_SSE_I387
   && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
   && GET_MODE (operands[0]) == GET_MODE (operands[1])"


(define_insn "*cmpfp_iu_mixed"
  [(set (reg:CCFPU FLAGS_REG)
	(compare:CCFPU (match_operand 0 "register_operand" "f,x")
		       (match_operand 1 "nonimmediate_operand" "f,xm")))]
  "TARGET_MIX_SSE_I387
   && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
   && GET_MODE (operands[0]) == GET_MODE (operands[1])"


(define_insn "*pushsf"
  [(set (match_operand:SF 0 "push_operand" "=<,<,<")
	(match_operand:SF 1 "general_no_elim_operand" "f,rFm,x"))]
  "!TARGET_64BIT"
{
  /* Anything else should be already split before reg-stack.  */


(define_insn "*pushsf_rex64"
  [(set (match_operand:SF 0 "push_operand" "=X,X,X")
	(match_operand:SF 1 "nonmemory_no_elim_operand" "f,rF,x"))]
  "TARGET_64BIT"
{
  /* Anything else should be already split before reg-stack.  */


(define_insn "*movsf_1"
  [(set (match_operand:SF 0 "nonimmediate_operand"
	  "=f,m   ,f,r,m    ,x,x,x,m   ,!*y,!rm,!*y")
	(match_operand:SF 1 "general_operand"
	  "fm,f,G   ,rmF,Fr,C   ,x   ,xm,x,rm ,*y ,*y"))]
  "!(MEM_P (operands[0]) && MEM_P (operands[1]))
   && (reload_in_progress || reload_completed
       || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)


(define_insn "*pushdf_nointeger"
  [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
	(match_operand:DF 1 "general_no_elim_operand" "f,Fo,*r,Y"))]
  "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
{
  /* This insn should be already split before reg-stack.  */


(define_insn "*pushdf_integer"
  [(set (match_operand:DF 0 "push_operand" "=<,<,<")
	(match_operand:DF 1 "general_no_elim_operand" "f,rFo,Y"))]
  "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
{
  /* This insn should be already split before reg-stack.  */


(define_insn "*movdf_nointeger"
  [(set (match_operand:DF 0 "nonimmediate_operand"
			"=f,m  ,f,*r  ,o  ,Y*x,Y*x,Y*x,m    ")
	(match_operand:DF 1 "general_operand"
			"fm,f,G  ,*roF,F*r,C    ,Y*x,HmY*x,Y*x"))]
  "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
   && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
   && (reload_in_progress || reload_completed


(define_insn "*movdf_integer"
  [(set (match_operand:DF 0 "nonimmediate_operand"
		"=f,m   ,f,r,o    ,Y*x,Y*x,Y*x,m")
	(match_operand:DF 1 "general_operand"
		"fm,f,G   ,roF,Fr,C     ,Y*x,m     ,Y*x"))]
  "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
   && ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
   && (reload_in_progress || reload_completed


(define_insn "*pushxf_integer"
  [(set (match_operand:XF 0 "push_operand" "=<,<")
	(match_operand:XF 1 "general_no_elim_operand" "f,ro"))]
  "!optimize_size"
{
  /* This insn should be already split before reg-stack.  */

   (set_attr "mode" "XF,XF,XF,SI,SI")])

(define_insn "*movxf_integer"
  [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,r,o")
	(match_operand:XF 1 "general_operand" "fm,f,G,roF,Fr"))]
  "!optimize_size
   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
   && (reload_in_progress || reload_completed

})

(define_insn "*extendsfdf2_mixed"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m,Y")
        (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,f,mY")))]
  "TARGET_SSE2 && TARGET_MIX_SSE_I387
   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{

})

(define_insn "*truncxfsf2_mixed"
  [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f,?r,?x")
	(float_truncate:SF
	 (match_operand:XF 1 "register_operand" "f,f,f,f")))
   (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]

   (set_attr "mode" "SF")])

(define_insn "*truncxfsf2_i387"
  [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f,?r")
	(float_truncate:SF
	 (match_operand:XF 1 "register_operand" "f,f,f")))
   (clobber (match_operand:SF 2 "memory_operand" "=X,m,m"))]

})

(define_insn "*truncxfdf2_mixed"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f,?r,?Y")
	(float_truncate:DF
	 (match_operand:XF 1 "register_operand" "f,f,f,f")))
   (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]

   (set_attr "mode" "DF")])

(define_insn "*truncxfdf2_i387"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f,?r")
	(float_truncate:DF
	 (match_operand:XF 1 "register_operand" "f,f,f")))
   (clobber (match_operand:DF 2 "memory_operand" "=X,m,m"))]

  "")

(define_insn "*floatsisf2_mixed"
  [(set (match_operand:SF 0 "register_operand" "=f,?f,x,x")
	(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
  "TARGET_MIX_SSE_I387"
  "@

  "")

(define_insn "*floatdisf2_mixed"
  [(set (match_operand:SF 0 "register_operand" "=f,?f,x,x")
	(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
  "TARGET_64BIT && TARGET_MIX_SSE_I387"
  "@

  "")

(define_insn "*floatsidf2_mixed"
  [(set (match_operand:DF 0 "register_operand" "=f,?f,Y,Y")
	(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
  "TARGET_SSE2 && TARGET_MIX_SSE_I387"
  "@

  "")

(define_insn "*floatdidf2_mixed"
  [(set (match_operand:DF 0 "register_operand" "=f,?f,Y,Y")
	(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
  "TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387"
  "@

  "ix86_expand_fp_absneg_operator (ABS, SFmode, operands); DONE;")

(define_insn "*absnegsf2_mixed"
  [(set (match_operand:SF 0 "nonimmediate_operand"    "=x,x,f,rm")
	(match_operator:SF 3 "absneg_operator"
	  [(match_operand:SF 1 "nonimmediate_operand" "0   ,x,0  ,0")]))
   (use (match_operand:V4SF 2 "nonimmediate_operand"  "xm  ,0  ,X  ,X"))
   (clobber (reg:CC FLAGS_REG))]
  "TARGET_SSE_MATH && TARGET_MIX_SSE_I387

  "ix86_expand_fp_absneg_operator (ABS, DFmode, operands); DONE;")

(define_insn "*absnegdf2_mixed"
  [(set (match_operand:DF 0 "nonimmediate_operand"    "=Y,Y,f,rm")
	(match_operator:DF 3 "absneg_operator"
	  [(match_operand:DF 1 "nonimmediate_operand" "0   ,Y,0  ,0")]))
   (use (match_operand:V2DF 2 "nonimmediate_operand"  "Ym  ,0  ,X  ,X"))
   (clobber (reg:CC FLAGS_REG))]
  "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387

(define_insn "*fp_jcc_1_mixed"
  [(set (pc)
	(if_then_else (match_operator 0 "comparison_operator"
			[(match_operand 1 "register_operand" "f,x")
			 (match_operand 2 "nonimmediate_operand" "f,xm")])
	  (label_ref (match_operand 3 "" ""))
	  (pc)))
   (clobber (reg:CCFP FPSR_REG))

(define_insn "*fp_jcc_2_mixed"
  [(set (pc)
	(if_then_else (match_operator 0 "comparison_operator"
			[(match_operand 1 "register_operand" "f,x")
			 (match_operand 2 "nonimmediate_operand" "f,xm")])
	  (pc)
	  (label_ref (match_operand 3 "" ""))))
   (clobber (reg:CCFP FPSR_REG))

;; so use special patterns for add and mull.

(define_insn "*fop_sf_comm_mixed"
  [(set (match_operand:SF 0 "register_operand" "=f,x")
	(match_operator:SF 3 "binary_fp_operator"
			[(match_operand:SF 1 "nonimmediate_operand" "%0,0")
			 (match_operand:SF 2 "nonimmediate_operand" "fm,xm")]))]
  "TARGET_MIX_SSE_I387
   && COMMUTATIVE_ARITH_P (operands[3])
   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"

  [(set (match_operand:SF 0 "register_operand" "=f,f,x")
	(match_operator:SF 3 "binary_fp_operator"
			[(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
			 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm")]))]
  "TARGET_MIX_SSE_I387
   && !COMMUTATIVE_ARITH_P (operands[3])
   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"

   (set_attr "mode" "<MODE>")])

(define_insn "*fop_df_comm_mixed"
  [(set (match_operand:DF 0 "register_operand" "=f,Y")
	(match_operator:DF 3 "binary_fp_operator"
			[(match_operand:DF 1 "nonimmediate_operand" "%0,0")
			 (match_operand:DF 2 "nonimmediate_operand" "fm,Ym")]))]
  "TARGET_SSE2 && TARGET_MIX_SSE_I387
   && COMMUTATIVE_ARITH_P (operands[3])
   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"

   (set_attr "mode" "DF")])

(define_insn "*fop_df_1_mixed"
  [(set (match_operand:DF 0 "register_operand" "=f,f,Y")
	(match_operator:DF 3 "binary_fp_operator"
			[(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
			 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym")]))]
  "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
   && !COMMUTATIVE_ARITH_P (operands[3])
   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"

})

(define_insn "*sqrtsf2_mixed"
  [(set (match_operand:SF 0 "register_operand" "=f,x")
	(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0,xm")))]
  "TARGET_USE_FANCY_MATH_387 && TARGET_MIX_SSE_I387"
  "@
   fsqrt

})

(define_insn "*sqrtdf2_mixed"
  [(set (match_operand:DF 0 "register_operand" "=f,Y")
	(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0,Ym")))]
  "TARGET_USE_FANCY_MATH_387 && TARGET_SSE2 && TARGET_MIX_SSE_I387"
  "@
   fsqrt

  "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")

(define_insn "*movsfcc_1_387"
  [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
	(if_then_else:SF (match_operator 1 "fcmov_comparison_operator" 
				[(reg FLAGS_REG) (const_int 0)])
		      (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
		      (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
  "TARGET_80387 && TARGET_CMOVE
   && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
  "@

  "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")

(define_insn "*movdfcc_1"
  [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
	(if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 
				[(reg FLAGS_REG) (const_int 0)])
		      (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
		      (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
  "!TARGET_64BIT && TARGET_80387 && TARGET_CMOVE
   && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
  "@

   (set_attr "mode" "DF")])

(define_insn "*movdfcc_1_rex64"
  [(set (match_operand:DF 0 "register_operand" "=f,f,r,r")
	(if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 
				[(reg FLAGS_REG) (const_int 0)])
		      (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
		      (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
  "TARGET_64BIT && TARGET_80387 && TARGET_CMOVE
   && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
  "@

Return to bug 19653

Lines 15411-15425 Link Here

(-)config/i386/i386.c (-7 / +40 lines)
15411	enum reg_class	15411	enum reg_class
15412	ix86_preferred_reload_class (rtx x, enum reg_class class)	15412	ix86_preferred_reload_class (rtx x, enum reg_class class)
15413	{	15413	{
		15414	enum machine_mode mode = GET_MODE (x);
		15415
15414	/* We're only allowed to return a subclass of CLASS. Many of the	15416	/* We're only allowed to return a subclass of CLASS. Many of the
15415	following checks fail for NO_REGS, so eliminate that early. */	15417	following checks fail for NO_REGS, so eliminate that early. */
15416	if (class == NO_REGS)	15418	if (class == NO_REGS)
15417	return NO_REGS;	15419	return NO_REGS;
15418		15420
15419	/* All classes can load zeros. */	15421	/* All classes can load zeros. */
15420	if (x == CONST0_RTX (GET_MODE (x)))	15422	if (x == CONST0_RTX (mode))
15421	return class;	15423	return class;
15422		15424
		15425	/* Force constants into memory if we are loading into MMX or SSE registers,
		15426	because there are no MMX/SSE instructions to load from a constant. */
		15427	if (CONSTANT_P (x)
		15428	&& (MAYBE_MMX_CLASS_P (class) \|\| MAYBE_SSE_CLASS_P (class)))
		15429	return NO_REGS;
		15430
		15431	/* Prefer SSE regs only, if we can use them for math. */
		15432	if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
		15433	return SSE_CLASS_P (class) ? class : NO_REGS;
		15434
15423	/* Floating-point constants need more complex checks. */	15435	/* Floating-point constants need more complex checks. */
15424	if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)	15436	if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
15425	{	15437	{
Lines 15431-15438 Link Here
15431	zero above. We only want to wind up preferring 80387 registers if	15459	zero above. We only want to wind up preferring 80387 registers if
15432	we plan on doing computation with them. */	15460	we plan on doing computation with them. */
15433	if (TARGET_80387	15461	if (TARGET_80387
15434	&& (TARGET_MIX_SSE_I387
15435	\|\| !(TARGET_SSE_MATH && SSE_FLOAT_MODE_P (GET_MODE (x))))
15436	&& standard_80387_constant_p (x))	15462	&& standard_80387_constant_p (x))
15437	{	15463	{
15438	/* Limit class to non-sse. */	15464	/* Limit class to non-sse. */
Lines 15448-15457 Link Here
15448		15474
15449	return NO_REGS;	15475	return NO_REGS;
15450	}	15476	}
15451	if (MAYBE_MMX_CLASS_P (class) && CONSTANT_P (x))
15452	return NO_REGS;
15453	if (MAYBE_SSE_CLASS_P (class) && CONSTANT_P (x))
15454	return NO_REGS;
15455		15477
15456	/* Generally when we see PLUS here, it's the function invariant	15478	/* Generally when we see PLUS here, it's the function invariant
15457	(plus soft-fp const_int). Which can only be computed into general	15479	(plus soft-fp const_int). Which can only be computed into general
Lines 15473-15478 Link Here
15473	return class;	15495	return class;
15474	}	15496	}
15475		15497
		15498	/* Discourage putting floating-point values in SSE registers unless
		15499	SSE math is being used, and likewise for the 387 registers. */
		15500	enum reg_class
		15501	ix86_preferred_output_reload_class (rtx x, enum reg_class class)
		15502	{
		15503	enum machine_mode mode = GET_MODE (x);
		15504
		15505	/* Restrict the output reload class to the register bank that we are doing
		15506	math on. If we would like not to return a subset of CLASS, reject this
		15507	alternative: if reload cannot do this, it will still use its choice. */
		15508	mode = GET_MODE (x);
		15509	if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
		15510	return MAYBE_SSE_CLASS_P (class) ? SSE_REGS : NO_REGS;
		15511
		15512	if (TARGET_80387 && SCALAR_FLOAT_MODE_P (mode))
		15513	{
		15514	if (class == FP_TOP_SSE_REGS)
		15515	return FP_TOP_REG;
		15516	else if (class == FP_SECOND_SSE_REGS)
		15517	return FP_SECOND_REG;
		15518	else
		15519	return FLOAT_CLASS_P (class) ? class : NO_REGS;
		15520	}
		15521
		15522	return class;
		15523	}
		15524
15476	/* If we are copying between general and FP registers, we need a memory	15525	/* If we are copying between general and FP registers, we need a memory
15477	location. The same is true for SSE and MMX registers.	15526	location. The same is true for SSE and MMX registers.
15478		15527