Lines 529-545
(define_expand "divv2sf3"
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(match_operand:V2SF 2 "register_operand")))] |
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(match_operand:V2SF 2 "register_operand")))] |
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"TARGET_MMX_WITH_SSE" |
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"TARGET_MMX_WITH_SSE" |
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{ |
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{ |
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rtx op0 = lowpart_subreg (V4SFmode, operands[0], |
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rtx op1 = lowpart_subreg (V4SFmode, force_reg (V2SFmode, operands[1]), |
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GET_MODE (operands[0])); |
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V2SFmode); |
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rtx op1 = lowpart_subreg (V4SFmode, operands[1], |
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GET_MODE (operands[1])); |
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rtx op2 = gen_rtx_VEC_CONCAT (V4SFmode, operands[2], |
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rtx op2 = gen_rtx_VEC_CONCAT (V4SFmode, operands[2], |
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force_reg (V2SFmode, CONST1_RTX (V2SFmode))); |
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force_reg (V2SFmode, CONST1_RTX (V2SFmode))); |
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rtx tmp = gen_reg_rtx (V4SFmode); |
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rtx tmp = gen_reg_rtx (V4SFmode); |
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emit_insn (gen_rtx_SET (tmp, op2)); |
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emit_insn (gen_rtx_SET (tmp, op2)); |
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rtx op0 = gen_reg_rtx (V4SFmode); |
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emit_insn (gen_divv4sf3 (op0, op1, tmp)); |
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emit_insn (gen_divv4sf3 (op0, op1, tmp)); |
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emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode)); |
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DONE; |
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DONE; |
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}) |
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}) |
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