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(-)m68k.md (-11 / +40 lines)
Lines 3118-3139 Link Here
3118
;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
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;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
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;; proper matching constraint.  This is because the matching is between
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;; proper matching constraint.  This is because the matching is between
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;; the high-numbered word of the DImode operand[0] and operand[1].
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;; the high-numbered word of the DImode operand[0] and operand[1].
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;;
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;; Note: life_analysis() does not keep track of the individual halves of the
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;; DImode register.  To prevent spurious liveness before the u?mulsidi3 insn
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;; (which causes "uninitialized variable" warnings), we explicitly clobber
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;; the DImode register.
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(define_expand "umulsidi3"
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(define_expand "umulsidi3"
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  [(parallel
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  [(set (match_operand:DI 0 "register_operand" "")
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    [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
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	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
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	  (mult:SI (match_operand:SI 1 "register_operand" "")
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		 (zero_extend:DI (match_operand:SI 2 "register_operand" ""))))]
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		   (match_operand:SI 2 "register_operand" "")))
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  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
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  "")
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(define_insn_and_split "*umulsidi3_split"
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  [(set (match_operand:DI 0 "register_operand" "")
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	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
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		 (zero_extend:DI (match_operand:SI 2 "register_operand" ""))))]
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  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
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  "#"
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  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
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  [(clobber (match_dup 0))
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   (parallel
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    [(set (subreg:SI (match_dup 0) 4)
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	  (mult:SI (match_dup 1) (match_dup 2)))
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     (set (subreg:SI (match_dup 0) 0)
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     (set (subreg:SI (match_dup 0) 0)
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	  (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
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	  (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
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					     (zero_extend:DI (match_dup 2)))
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					     (zero_extend:DI (match_dup 2)))
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				    (const_int 32))))])]
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				    (const_int 32))))])]
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  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
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  "")
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  "")
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(define_insn ""
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(define_insn ""
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  [(set (match_operand:SI 0 "register_operand" "=d")
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  [(set (match_operand:SI 0 "register_operand" "=d")
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	(mult:SI (match_operand:SI 1 "register_operand" "%0")
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	(mult:SI (match_operand:SI 1 "register_operand" "%0")
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		  (match_operand:SI 2 "nonimmediate_operand" "dm")))
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		 (match_operand:SI 2 "nonimmediate_operand" "dm")))
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   (set (match_operand:SI 3 "register_operand" "=d")
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   (set (match_operand:SI 3 "register_operand" "=d")
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	(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
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	(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
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					   (zero_extend:DI (match_dup 2)))
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					   (zero_extend:DI (match_dup 2)))
Lines 3158-3172 Link Here
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  "mulu%.l %2,%3:%0")
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  "mulu%.l %2,%3:%0")
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(define_expand "mulsidi3"
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(define_expand "mulsidi3"
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  [(parallel
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  [(set (match_operand:DI 0 "register_operand" "")
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    [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
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	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
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	  (mult:SI (match_operand:SI 1 "register_operand" "")
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		 (sign_extend:DI (match_operand:SI 2 "register_operand" ""))))]
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		   (match_operand:SI 2 "register_operand" "")))
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  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
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  "")
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(define_insn_and_split "*mulsidi3_split"
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  [(set (match_operand:DI 0 "register_operand" "")
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	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
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		 (sign_extend:DI (match_operand:SI 2 "register_operand" ""))))]
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  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
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  "#"
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  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
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  [(clobber (match_dup 0))
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   (parallel
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    [(set (subreg:SI (match_dup 0) 4)
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	  (mult:SI (match_dup 1) (match_dup 2)))
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     (set (subreg:SI (match_dup 0) 0)
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     (set (subreg:SI (match_dup 0) 0)
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	  (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
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	  (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
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					     (sign_extend:DI (match_dup 2)))
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					     (sign_extend:DI (match_dup 2)))
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				    (const_int 32))))])]
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				    (const_int 32))))])]
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  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
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  "")
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  "")
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(define_insn ""
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(define_insn ""

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