diff --git a/home/levy/Desktop/Compare/riscv-gnu-toolchain/riscv-gcc/gcc/combine.c b/home/levy/Desktop/riscv-gnu-toolchain/riscv-gcc/gcc/combine.c
index f69413a..6fced9b 100644
--- a/home/levy/Desktop/Compare/riscv-gnu-toolchain/riscv-gcc/gcc/combine.c
+++ b/home/levy/Desktop/riscv-gnu-toolchain/riscv-gcc/gcc/combine.c
@@ -2635,6 +2635,22 @@ is_just_move (rtx x)
   return (GET_CODE (x) == SET && general_operand (SET_SRC (x), VOIDmode));
 }
 
+/* Return whether X is just a single set, with the source
+   a sign/zero extended general_operand.  */
+static bool
+is_just_extended_move (rtx x)
+{
+  if (INSN_P (x))
+    x = PATTERN (x);
+
+  if(GET_CODE (x) == SET)
+      if (GET_CODE (SET_SRC (x)) == ZERO_EXTEND 
+	      || GET_CODE (SET_SRC (x)) == SIGN_EXTEND)
+		return (general_operand ((XEXP (SET_SRC (x), 0)), VOIDmode));
+
+  return (GET_CODE (x) == SET && general_operand (SET_SRC (x), VOIDmode));
+}
+
 /* Callback function to count autoincs.  */
 
 static int
@@ -3103,8 +3119,8 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
     }
 
   /* Record whether i2 and i3 are trivial moves.  */
-  i2_was_move = is_just_move (i2);
-  i3_was_move = is_just_move (i3);
+  i2_was_move = is_just_move (i2) || is_just_extended_move(i2);
+  i3_was_move = is_just_move (i3) || is_just_extended_move(i3);
 
   /* Record whether I2DEST is used in I2SRC and similarly for the other
      cases.  Knowing this will help in register status updating below.  */
diff --git a/home/levy/Desktop/Compare/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv-shorten-memrefs.c b/home/levy/Desktop/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv-shorten-memrefs.c
index 3686005..9a2e038 100644
--- a/home/levy/Desktop/Compare/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv-shorten-memrefs.c
+++ b/home/levy/Desktop/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv-shorten-memrefs.c
@@ -75,12 +75,19 @@ private:
 
   regno_map * analyze (basic_block bb);
   void transform (regno_map *m, basic_block bb);
-  bool get_si_mem_base_reg (rtx mem, rtx *addr);
+  bool get_si_mem_base_reg (rtx mem, rtx *addr, bool *extend);
 }; // class pass_shorten_memrefs
 
 bool
-pass_shorten_memrefs::get_si_mem_base_reg (rtx mem, rtx *addr)
+pass_shorten_memrefs::get_si_mem_base_reg (rtx mem, rtx *addr, bool *extend)
 {
+  /* Whether it's sign/zero extended  */
+    if (GET_CODE (mem) == ZERO_EXTEND || GET_CODE (mem) == SIGN_EXTEND)
+  {
+    *extend = true;
+    mem = XEXP (mem, 0);
+  }
+
   if (!MEM_P (mem) || GET_MODE (mem) != SImode)
     return false;
   *addr = XEXP (mem, 0);
@@ -110,7 +117,8 @@ pass_shorten_memrefs::analyze (basic_block bb)
 	{
 	  rtx mem = XEXP (pat, i);
 	  rtx addr;
-	  if (get_si_mem_base_reg (mem, &addr))
+      bool extend = false;
+	  if (get_si_mem_base_reg (mem, &addr, &extend))
 	    {
 	      HOST_WIDE_INT regno = REGNO (XEXP (addr, 0));
 	      /* Do not count store zero as these cannot be compressed.  */
@@ -150,7 +158,8 @@ pass_shorten_memrefs::transform (regno_map *m, basic_block bb)
 	{
 	  rtx mem = XEXP (pat, i);
 	  rtx addr;
-	  if (get_si_mem_base_reg (mem, &addr))
+      bool extend = false;
+	  if (get_si_mem_base_reg (mem, &addr, &extend))
 	    {
 	      HOST_WIDE_INT regno = REGNO (XEXP (addr, 0));
 	      /* Do not transform store zero as these cannot be compressed.  */
@@ -161,10 +170,17 @@ pass_shorten_memrefs::transform (regno_map *m, basic_block bb)
 		}
 	      if (m->get_or_insert (regno) > 3)
 		{
-		  addr
-		    = targetm.legitimize_address (addr, addr, GET_MODE (mem));
-		  XEXP (pat, i) = replace_equiv_address (mem, addr);
-		  df_insn_rescan (insn);
+        if (extend)
+        {
+          addr = targetm.legitimize_address (addr, addr, GET_MODE (XEXP (mem, 0)));
+          XEXP (XEXP (pat, i), 0) = replace_equiv_address (XEXP (mem, 0), addr);
+        }
+        else
+        {
+          addr = targetm.legitimize_address (addr, addr, GET_MODE (mem));
+          XEXP (pat, i) = replace_equiv_address (mem, addr);
+        }
+		    df_insn_rescan (insn);
 		}
 	    }
 	}
diff --git a/home/levy/Desktop/Compare/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv.c b/home/levy/Desktop/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv.c
index d489717..23107fc 100644
--- a/home/levy/Desktop/Compare/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv.c
+++ b/home/levy/Desktop/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv.c
@@ -1528,6 +1528,28 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
 bool
 riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
 {
+  /* Expand 
+    (set (reg:QI target) (mem:QI (address))) 
+      to
+    (set (reg:DI temp) (zero_extend:DI (mem:DI (address))))
+    (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
+      with auto-sign/zero extend.  */
+  if (GET_MODE_CLASS (mode) == MODE_INT
+      && GET_MODE_SIZE (mode) < UNITS_PER_WORD
+      && can_create_pseudo_p()
+      && MEM_P (src))
+    {
+      rtx temp_reg;
+      int zero_sign_extend;
+
+      temp_reg = gen_reg_rtx (word_mode);
+      zero_sign_extend = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND);
+      emit_insn (gen_extend_insn(temp_reg, src, word_mode, mode, 
+                 zero_sign_extend));
+      riscv_emit_move (dest, gen_lowpart(mode, temp_reg));
+      return true;
+    }
+
   if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
     {
       rtx reg;