GCC Bugzilla – Attachment 49575 Details for
Bug 97417
RISC-V Unnecessary andi instruction when loading volatile bool
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[patch]
riscv-shorten-memrefs_V1.patch
riscv-shorten-memrefs_V1.patch (text/plain), 3.45 KB, created by
Levy Hsu
on 2020-11-17 10:19:18 UTC
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Description:
riscv-shorten-memrefs_V1.patch
Filename:
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Creator:
Levy Hsu
Created:
2020-11-17 10:19:18 UTC
Size:
3.45 KB
patch
obsolete
>diff --git a/home/levy/Desktop/original_tool_chain/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv-shorten-memrefs.c b/home/levy/Desktop/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv-shorten-memrefs.c >index 3686005..aa3a097 100644 >--- a/home/levy/Desktop/original_tool_chain/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv-shorten-memrefs.c >+++ b/home/levy/Desktop/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv-shorten-memrefs.c >@@ -75,14 +75,22 @@ private: > > regno_map * analyze (basic_block bb); > void transform (regno_map *m, basic_block bb); >- bool get_si_mem_base_reg (rtx mem, rtx *addr); >+ bool get_si_mem_base_reg (rtx mem, rtx *addr, int *extend); > }; // class pass_shorten_memrefs > > bool >-pass_shorten_memrefs::get_si_mem_base_reg (rtx mem, rtx *addr) >+pass_shorten_memrefs::get_si_mem_base_reg (rtx mem, rtx *addr, int *extend) > { >+ /* For ::transform(), Check extention, return by *extend, >+ 1 for zero extend, 2 for sign extend */ >+ if (GET_CODE (mem) == ZERO_EXTEND || GET_CODE (mem) == SIGN_EXTEND) >+ { >+ *extend = (GET_CODE (mem) == ZERO_EXTEND)?1:2; >+ mem = XEXP (mem, 0); >+ } >+ > if (!MEM_P (mem) || GET_MODE (mem) != SImode) >- return false; >+ return false; > *addr = XEXP (mem, 0); > return GET_CODE (*addr) == PLUS && REG_P (XEXP (*addr, 0)); > } >@@ -110,7 +118,8 @@ pass_shorten_memrefs::analyze (basic_block bb) > { > rtx mem = XEXP (pat, i); > rtx addr; >- if (get_si_mem_base_reg (mem, &addr)) >+ int extend = 0; >+ if (get_si_mem_base_reg (mem, &addr, &extend)) > { > HOST_WIDE_INT regno = REGNO (XEXP (addr, 0)); > /* Do not count store zero as these cannot be compressed. */ >@@ -150,7 +159,8 @@ pass_shorten_memrefs::transform (regno_map *m, basic_block bb) > { > rtx mem = XEXP (pat, i); > rtx addr; >- if (get_si_mem_base_reg (mem, &addr)) >+ int extend = 0; >+ if (get_si_mem_base_reg (mem, &addr, &extend)) > { > HOST_WIDE_INT regno = REGNO (XEXP (addr, 0)); > /* Do not transform store zero as these cannot be compressed. */ >@@ -161,9 +171,40 @@ pass_shorten_memrefs::transform (regno_map *m, basic_block bb) > } > if (m->get_or_insert (regno) > 3) > { >- addr >- = targetm.legitimize_address (addr, addr, GET_MODE (mem)); >- XEXP (pat, i) = replace_equiv_address (mem, addr); >+ switch (extend) >+ { >+ case 0: >+ addr = targetm.legitimize_address (addr, addr, GET_MODE (mem)); >+ XEXP (pat, i) = replace_equiv_address (mem, addr); >+ break; >+ case 1: >+ addr = targetm.legitimize_address (addr, addr, GET_MODE (XEXP (mem, 0))); >+ /* >+ debug_rtx (addr); >+ debug_rtx (XEXP (pat, i)); >+ debug_rtx (XEXP (XEXP (pat, i),0)); >+ debug_rtx (mem); >+ debug_rtx (XEXP (mem, 0)); >+ */ >+ XEXP (XEXP (pat, i), 0) = replace_equiv_address (XEXP (mem, 0), addr); >+ debug_rtx(pat); >+ break; >+ case 2: >+ addr = targetm.legitimize_address (addr, addr, GET_MODE (XEXP (mem, 0))); >+ /* >+ debug_rtx (addr); >+ debug_rtx (XEXP (pat, i)); >+ debug_rtx (XEXP (XEXP (pat, i),0)); >+ debug_rtx (mem); >+ debug_rtx (XEXP (mem, 0)); >+ */ >+ XEXP (XEXP (pat, i), 0) = replace_equiv_address (XEXP (mem, 0), addr); >+ debug_rtx(pat); >+ break; >+ default: >+ gcc_assert(PATTERN (insn)); >+ break; >+ } > df_insn_rescan (insn); > } > }
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bug 97417
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49470
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49575
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49757
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49767
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49773