diff --git a/riscv-gcc/gcc/config/riscv/riscv.c b/home/levy/Desktop/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv.c
index d489717..c38e372 100644
--- a/riscv-gcc/gcc/config/riscv/riscv.c
+++ b/home/levy/Desktop/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv.c
@@ -1528,6 +1528,28 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
 bool
 riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
 {
+  /* Expand 
+      (set (reg:QI target) (mem:QI (address))) 
+        to
+      (set (reg:DI temp) (zero_extend:DI (mem:DI (address))))
+      (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
+    with auto-sign/zero extend.  */
+
+  if (GET_MODE_CLASS (mode) == MODE_INT
+        && GET_MODE_SIZE (mode) < UNITS_PER_WORD
+        && can_create_pseudo_p()
+        && MEM_P (src))
+    {
+      rtx temp_reg;
+      int zero_sign_extend;
+
+      temp_reg = gen_reg_rtx (word_mode);
+      zero_sign_extend = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND);
+      emit_insn (gen_extend_insn(temp_reg, src, word_mode, mode, zero_sign_extend));
+      riscv_emit_move (dest, gen_lowpart(mode, temp_reg));
+      return true;
+    }
+
   if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
     {
       rtx reg;