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Lines 1528-1533
riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
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| 1528 |
bool |
1528 |
bool |
| 1529 |
riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) |
1529 |
riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) |
| 1530 |
{ |
1530 |
{ |
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1531 |
/* Expand (set (reg:QI target) (mem:QI (address))) |
| 1532 |
to |
| 1533 |
(set (reg:DI temp) (zero_extend:DI (mem:DI (address)))) |
| 1534 |
(set (reg:QI target) (subreg:QI (reg:DI temp) 0)) |
| 1535 |
with auto-sign/zero extend. */ |
| 1536 |
|
| 1537 |
if (GET_MODE_CLASS (mode) == MODE_INT |
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&& GET_MODE_SIZE (mode) < UNITS_PER_WORD |
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&& can_create_pseudo_p() |
| 1540 |
&& MEM_P (src)) |
| 1541 |
{ |
| 1542 |
rtx temp_reg; |
| 1543 |
int zero_sign_extend; |
| 1544 |
|
| 1545 |
temp_reg = gen_reg_rtx (word_mode); |
| 1546 |
zero_sign_extend = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND); |
| 1547 |
emit_insn (gen_extend_insn(temp_reg, src, word_mode, mode, zero_sign_extend)); |
| 1548 |
riscv_emit_move (dest, gen_lowpart(mode, temp_reg)); |
| 1549 |
return true; |
| 1550 |
} |
| 1551 |
|
| 1531 |
if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode)) |
1552 |
if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode)) |
| 1532 |
{ |
1553 |
{ |
| 1533 |
rtx reg; |
1554 |
rtx reg; |