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(-)a/riscv-gcc/gcc/config/riscv/riscv.c (+21 lines)
Lines 1528-1533 riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) Link Here
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bool
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bool
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riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
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riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
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{
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{
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    /* Expand (set (reg:QI target) (mem:QI (address))) 
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          to
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        (set (reg:DI temp) (zero_extend:DI (mem:DI (address))))
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        (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
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        with auto-sign/zero extend. */
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  if (GET_MODE_CLASS (mode) == MODE_INT
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        && GET_MODE_SIZE (mode) < UNITS_PER_WORD
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        && can_create_pseudo_p()
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        && MEM_P (src))
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  {
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      rtx temp_reg;
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      int zero_sign_extend;
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      temp_reg = gen_reg_rtx (word_mode);
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      zero_sign_extend = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND);
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      emit_insn (gen_extend_insn(temp_reg, src, word_mode, mode, zero_sign_extend));
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      riscv_emit_move (dest, gen_lowpart(mode, temp_reg));
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      return true;
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  }
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  if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
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  if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
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    {
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    {
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      rtx reg;
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      rtx reg;

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