Attachment 49536 Details for Bug 97417 – QI/HI/SImode auto Zero/Sign-extend

[patch] QI/HI/SImode auto Zero/Sign-extend

97417_5.patch (text/plain), 1.15 KB, created by Levy Hsu on 2020-11-10 10:47:01 UTC

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Creator: Levy Hsu

Created: 2020-11-10 10:47:01 UTC

Size: 1.15 KB

patch

obsolete

>diff --git a/riscv-gcc/gcc/config/riscv/riscv.c b/home/levy/Desktop/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv.c
>index d489717..6601468 100644
>--- a/riscv-gcc/gcc/config/riscv/riscv.c
>+++ b/home/levy/Desktop/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv.c
>@@ -1528,6 +1528,24 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
> bool
> riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
> {
>+  /* Seperate (set (reg:QI target) (mem:QI (address))) 
>+    to
>+    (set (reg:DI temp) (zero_extend:DI (mem:DI (address))))
>+    (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
>+    with auto-sign extend */
>+
>+  if (GET_MODE_CLASS (mode) == MODE_INT
>+	    && GET_MODE_SIZE (mode) < UNITS_PER_WORD
>+      && can_create_pseudo_p()
>+      && MEM_P (src))
>+  {
>+      rtx temp_reg = gen_reg_rtx (word_mode);
>+      int zero_sign_extend = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND);
>+      emit_insn(gen_extend_insn(temp_reg, src, word_mode, mode, zero_sign_extend));
>+      riscv_emit_move(dest, gen_lowpart(mode, temp_reg));
>+      return true;
>+  }
>+
>   if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
>     {
>       rtx reg;

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Attachments on bug 97417: 49470 | 49500 | 49524 | 49532 | 49533 | 49534 | 49536 | 49542 | 49543 | 49575 | 49757 | 49767 | 49773