Attachment #49534 for bug #97417

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Lines 48-53 extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *, bool); Link Here

(-)a/riscv-gcc/gcc/config/riscv/riscv-protos.h (+1 lines)
48	extern bool riscv_split_symbol_type (enum riscv_symbol_type);	48	extern bool riscv_split_symbol_type (enum riscv_symbol_type);
49	extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);	49	extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
50	extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode, bool);	50	extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode, bool);
		51	extern bool gen_extend_insn_auto(machine_mode, machine_mode, rtx, rtx, int);
51	extern bool riscv_legitimize_move (machine_mode, rtx, rtx);	52	extern bool riscv_legitimize_move (machine_mode, rtx, rtx);
52	extern rtx riscv_subword (rtx, bool);	53	extern rtx riscv_subword (rtx, bool);
53	extern bool riscv_split_64bit_move_p (rtx, rtx);	54	extern bool riscv_split_64bit_move_p (rtx, rtx);




  riscv_emit_move (dest, src);
}

/* Seperate (set (reg:QI target) (mem:QI (address))) 
    to
    (set (reg:DI temp) (zero_extend:DI (mem:DI (address))))
  (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
  with auto-sign extend */

bool 
gen_extend_insn_auto (machine_mode mode, 
      machine_mode current_word_mode, rtx dest, rtx src, int unsignedp)
{
  rtx temp_reg;
  switch(current_word_mode)
  {
    /* RV32 */
    case SImode:
    {
      switch(mode)
      {
        case QImode:
        {
          temp_reg = gen_reg_rtx (SImode);
          if (unsignedp)
              emit_insn(gen_zero_extendqisi2 (temp_reg, src));
          else
              emit_insn(gen_extendqisi2 (temp_reg, src));
          riscv_emit_move(dest, gen_lowpart(QImode, temp_reg));
          return true;
        }
        case HImode:
        {
          temp_reg = gen_reg_rtx (SImode);
          if (unsignedp)
              emit_insn(gen_zero_extendhisi2 (temp_reg, src));
          else
              emit_insn(gen_extendhisi2 (temp_reg, src));
          riscv_emit_move(dest, gen_lowpart(HImode, temp_reg));
          return true;
        }
      }
    }
    /* RV64 */
    case DImode:
    {
      switch(mode)
      {
        case QImode:
        {
          temp_reg = gen_reg_rtx (DImode);
          if (unsignedp)
              emit_insn(gen_zero_extendqidi2 (temp_reg, src));
          else
              emit_insn(gen_extendqidi2 (temp_reg, src));
          riscv_emit_move(dest, gen_lowpart(QImode, temp_reg));
          return true;
        }
        case HImode:
        {
          temp_reg = gen_reg_rtx (DImode);
          if (unsignedp)
              emit_insn(gen_zero_extendhidi2 (temp_reg, src));
          else
              emit_insn(gen_extendhidi2 (temp_reg, src));
          riscv_emit_move(dest, gen_lowpart(HImode, temp_reg));
          return true;
        }
        case SImode:
        {
          temp_reg = gen_reg_rtx (DImode);
          if (unsignedp)
              emit_insn(gen_zero_extendsidi2 (temp_reg, src));
          else
              emit_insn(gen_extendsidi2 (temp_reg, src));
          riscv_emit_move(dest, gen_lowpart(SImode, temp_reg));
          return true;
        }
      }
    }
    /* RV128 pre-implemented
    case OImode:
    {
      switch(mode)
      {
        case QImode:
        {
          temp_reg = gen_reg_rtx (OImode);
          if (unsignedp)
              emit_insn(gen_zero_extendqioi2 (temp_reg, src));
          else
              emit_insn(gen_extendqioi2 (temp_reg, src));
          riscv_emit_move(dest, gen_lowpart(QImode, temp_reg));
          return true;
        }
        case HImode:
        {
          temp_reg = gen_reg_rtx (OImode);
          if (unsignedp)
              emit_insn(gen_zero_extendhioi2 (temp_reg, src));
          else
              emit_insn(gen_extendhioi2 (temp_reg, src));
          riscv_emit_move(dest, gen_lowpart(HImode, temp_reg));
          return true;
        }
        case SImode:
        {
          temp_reg = gen_reg_rtx (OImode);
          if (unsignedp)
              emit_insn(gen_zero_extendsioi2 (temp_reg, src));
          else
              emit_insn(gen_extendsioi2 (temp_reg, src));
          riscv_emit_move(dest, gen_lowpart(SImode, temp_reg));
          return true;
        }
        case DImode:
        {
          temp_reg = gen_reg_rtx (OImode);
          if (unsignedp)
              emit_insn(gen_zero_extenddioi2 (temp_reg, src));
          else
              emit_insn(gen_extenddioi2 (temp_reg, src));
          riscv_emit_move(dest, gen_lowpart(SImode, temp_reg));
          return true;
        }
      }
    }
    */
  return false;
  }
}

/* If (set DEST SRC) is not a valid move instruction, emit an equivalent
   sequence that is valid.  */

bool
riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
{
  /* Seperate (set (reg:QI target) (mem:QI (address))) 
    to
    (set (reg:DI temp) (zero_extend:DI (mem:DI (address))))
    (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
    with auto-sign extend */

  if (GET_MODE_CLASS (mode) == MODE_INT
	    && GET_MODE_SIZE (mode) < UNITS_PER_WORD
      && can_create_pseudo_p()
      && MEM_P (src))
  {
      int extend = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND);
      
      if (gen_extend_insn_auto (mode, word_mode, dest, src, extend))
          return true;
  }

  if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
    {
      rtx reg;

Return to bug 97417

Lines 1522-1533 riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) Link Here

(-)a/riscv-gcc/gcc/config/riscv/riscv.c (+146 lines)
1522	riscv_emit_move (dest, src);	1522	riscv_emit_move (dest, src);
1523	}	1523	}
1524		1524
		1525	/* Seperate (set (reg:QI target) (mem:QI (address)))
		1526	to
		1527	(set (reg:DI temp) (zero_extend:DI (mem:DI (address))))
		1528	(set (reg:QI target) (subreg:QI (reg:DI temp) 0))
		1529	with auto-sign extend */
		1530
		1531	bool
		1532	gen_extend_insn_auto (machine_mode mode,
		1533	machine_mode current_word_mode, rtx dest, rtx src, int unsignedp)
		1534	{
		1535	rtx temp_reg;
		1536	switch(current_word_mode)
		1537	{
		1538	/* RV32 */
		1539	case SImode:
		1540	{
		1541	switch(mode)
		1542	{
		1543	case QImode:
		1544	{
		1545	temp_reg = gen_reg_rtx (SImode);
		1546	if (unsignedp)
		1547	emit_insn(gen_zero_extendqisi2 (temp_reg, src));
		1548	else
		1549	emit_insn(gen_extendqisi2 (temp_reg, src));
		1550	riscv_emit_move(dest, gen_lowpart(QImode, temp_reg));
		1551	return true;
		1552	}
		1553	case HImode:
		1554	{
		1555	temp_reg = gen_reg_rtx (SImode);
		1556	if (unsignedp)
		1557	emit_insn(gen_zero_extendhisi2 (temp_reg, src));
		1558	else
		1559	emit_insn(gen_extendhisi2 (temp_reg, src));
		1560	riscv_emit_move(dest, gen_lowpart(HImode, temp_reg));
		1561	return true;
		1562	}
		1563	}
		1564	}
		1565	/* RV64 */
		1566	case DImode:
		1567	{
		1568	switch(mode)
		1569	{
		1570	case QImode:
		1571	{
		1572	temp_reg = gen_reg_rtx (DImode);
		1573	if (unsignedp)
		1574	emit_insn(gen_zero_extendqidi2 (temp_reg, src));
		1575	else
		1576	emit_insn(gen_extendqidi2 (temp_reg, src));
		1577	riscv_emit_move(dest, gen_lowpart(QImode, temp_reg));
		1578	return true;
		1579	}
		1580	case HImode:
		1581	{
		1582	temp_reg = gen_reg_rtx (DImode);
		1583	if (unsignedp)
		1584	emit_insn(gen_zero_extendhidi2 (temp_reg, src));
		1585	else
		1586	emit_insn(gen_extendhidi2 (temp_reg, src));
		1587	riscv_emit_move(dest, gen_lowpart(HImode, temp_reg));
		1588	return true;
1589	}
1590	case SImode:
1591	{
1592	temp_reg = gen_reg_rtx (DImode);
1593	if (unsignedp)
1594	emit_insn(gen_zero_extendsidi2 (temp_reg, src));
1595	else
1596	emit_insn(gen_extendsidi2 (temp_reg, src));
1597	riscv_emit_move(dest, gen_lowpart(SImode, temp_reg));
1598	return true;
1599	}
1600	}
1601	}
1602	/* RV128 pre-implemented
1603	case OImode:
1604	{
1605	switch(mode)
1606	{
1607	case QImode:
1608	{
1609	temp_reg = gen_reg_rtx (OImode);
1610	if (unsignedp)
1611	emit_insn(gen_zero_extendqioi2 (temp_reg, src));
1612	else
1613	emit_insn(gen_extendqioi2 (temp_reg, src));
1614	riscv_emit_move(dest, gen_lowpart(QImode, temp_reg));
1615	return true;
1616	}
1617	case HImode:
1618	{
1619	temp_reg = gen_reg_rtx (OImode);
1620	if (unsignedp)
1621	emit_insn(gen_zero_extendhioi2 (temp_reg, src));
1622	else
1623	emit_insn(gen_extendhioi2 (temp_reg, src));
1624	riscv_emit_move(dest, gen_lowpart(HImode, temp_reg));
1625	return true;
1626	}
1627	case SImode:
1628	{
1629	temp_reg = gen_reg_rtx (OImode);
1630	if (unsignedp)
1631	emit_insn(gen_zero_extendsioi2 (temp_reg, src));
1632	else
1633	emit_insn(gen_extendsioi2 (temp_reg, src));
1634	riscv_emit_move(dest, gen_lowpart(SImode, temp_reg));
1635	return true;
1636	}
1637	case DImode:
1638	{
1639	temp_reg = gen_reg_rtx (OImode);
1640	if (unsignedp)
1641	emit_insn(gen_zero_extenddioi2 (temp_reg, src));
1642	else
1643	emit_insn(gen_extenddioi2 (temp_reg, src));
1644	riscv_emit_move(dest, gen_lowpart(SImode, temp_reg));
1645	return true;
1646	}
1647	}
1648	}
1649	*/
1650	return false;
1651	}
1652	}
1653
1525	/* If (set DEST SRC) is not a valid move instruction, emit an equivalent	1654	/* If (set DEST SRC) is not a valid move instruction, emit an equivalent
1526	sequence that is valid. */	1655	sequence that is valid. */
1527		1656
1528	bool	1657	bool
1529	riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)	1658	riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
1530	{	1659	{
		1660	/* Seperate (set (reg:QI target) (mem:QI (address)))
		1661	to
		1662	(set (reg:DI temp) (zero_extend:DI (mem:DI (address))))
		1663	(set (reg:QI target) (subreg:QI (reg:DI temp) 0))
		1664	with auto-sign extend */
		1665
		1666	if (GET_MODE_CLASS (mode) == MODE_INT
		1667	&& GET_MODE_SIZE (mode) < UNITS_PER_WORD
		1668	&& can_create_pseudo_p()
		1669	&& MEM_P (src))
		1670	{
		1671	int extend = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND);
		1672
		1673	if (gen_extend_insn_auto (mode, word_mode, dest, src, extend))
		1674	return true;
		1675	}
		1676
1531	if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))	1677	if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
1532	{	1678	{
1533	rtx reg;	1679	rtx reg;