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(-)a/riscv-gcc/gcc/config/riscv/riscv.c (+17 lines)
Lines 1528-1533 riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) Link Here
1528
bool
1528
bool
1529
riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
1529
riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
1530
{
1530
{
1531
  /* Seperate (set (reg:QI target) (mem:QI (address))) 
1532
    to
1533
    (set (reg:DI temp) (zero_extend:DI (mem:DI (address))))
1534
    (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
1535
    with auto-sign extend */
1536
    
1537
  if (GET_MODE_CLASS (mode) == MODE_INT
1538
	    && GET_MODE_SIZE (mode) < UNITS_PER_WORD
1539
      && can_create_pseudo_p()
1540
      && MEM_P (src))
1541
  {
1542
      int extend = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND);
1543
      
1544
      if (gen_extend_insn_auto (mode, word_mode, dest, src, extend))
1545
          return true;
1546
  }
1547
1531
  if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
1548
  if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
1532
    {
1549
    {
1533
      rtx reg;
1550
      rtx reg;
(-)a/riscv-gcc/gcc/optabs.c (-2 / +131 lines)
Lines 4737-4743 have_sub2_insn (rtx x, rtx y) Link Here
4737
4737
4738
  return 1;
4738
  return 1;
4739
}
4739
}
4740
4740
4741
/* Generate the body of an insn to extend Y (with mode MFROM)
4741
/* Generate the body of an insn to extend Y (with mode MFROM)
4742
   into X (with mode MTO).  Do zero-extension if UNSIGNEDP is nonzero.  */
4742
   into X (with mode MTO).  Do zero-extension if UNSIGNEDP is nonzero.  */
4743
4743
Lines 4748-4754 gen_extend_insn (rtx x, rtx y, machine_mode mto, Link Here
4748
  enum insn_code icode = can_extend_p (mto, mfrom, unsignedp);
4748
  enum insn_code icode = can_extend_p (mto, mfrom, unsignedp);
4749
  return GEN_FCN (icode) (x, y);
4749
  return GEN_FCN (icode) (x, y);
4750
}
4750
}
4751
4751
4752
/* Seperate (set (reg:QI target) (mem:QI (address))) 
4753
    to
4754
    (set (reg:DI temp) (zero_extend:DI (mem:DI (address))))
4755
  (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
4756
  with auto-sign extend */
4757
4758
bool 
4759
gen_extend_insn_auto (machine_mode mode, 
4760
      machine_mode current_word_mode, rtx dest, rtx src, int unsignedp)
4761
{
4762
  rtx temp_reg;
4763
  switch(current_word_mode)
4764
  {
4765
    /* RV32 */
4766
    case SImode:
4767
    {
4768
      switch(mode)
4769
      {
4770
        case QImode:
4771
        {
4772
          temp_reg = gen_reg_rtx (DImode);
4773
          if (unsignedp)
4774
              emit_insn(gen_zero_extendqisi2 (temp_reg, src));
4775
          else
4776
              emit_insn(gen_extendqisi2 (temp_reg, src));
4777
          riscv_emit_move(dest, gen_lowpart(QImode, temp_reg));
4778
          return true;
4779
        }
4780
        case HImode:
4781
        {
4782
          temp_reg = gen_reg_rtx (DImode);
4783
          if (unsignedp)
4784
              emit_insn(gen_zero_extendhisi2 (temp_reg, src));
4785
          else
4786
              emit_insn(gen_extendhisi2 (temp_reg, src));
4787
          riscv_emit_move(dest, gen_lowpart(HImode, temp_reg));
4788
          return true;
4789
        }
4790
      }
4791
    }
4792
    /* RV64 */
4793
    case DImode:
4794
    {
4795
      switch(mode)
4796
      {
4797
        case QImode:
4798
        {
4799
          temp_reg = gen_reg_rtx (DImode);
4800
          if (unsignedp)
4801
              emit_insn(gen_zero_extendqidi2 (temp_reg, src));
4802
          else
4803
              emit_insn(gen_extendqidi2 (temp_reg, src));
4804
          riscv_emit_move(dest, gen_lowpart(QImode, temp_reg));
4805
          return true;
4806
        }
4807
        case HImode:
4808
        {
4809
          temp_reg = gen_reg_rtx (DImode);
4810
          if (unsignedp)
4811
              emit_insn(gen_zero_extendhidi2 (temp_reg, src));
4812
          else
4813
              emit_insn(gen_extendhidi2 (temp_reg, src));
4814
          riscv_emit_move(dest, gen_lowpart(HImode, temp_reg));
4815
          return true;
4816
        }
4817
        case SImode:
4818
        {
4819
          temp_reg = gen_reg_rtx (DImode);
4820
          if (unsignedp)
4821
              emit_insn(gen_zero_extendsidi2 (temp_reg, src));
4822
          else
4823
              emit_insn(gen_extendsidi2 (temp_reg, src));
4824
          riscv_emit_move(dest, gen_lowpart(SImode, temp_reg));
4825
          return true;
4826
        }
4827
      }
4828
    }
4829
    /* RV128 pre-implemented
4830
    case OImode:
4831
    {
4832
      switch(mode)
4833
      {
4834
        case QImode:
4835
        {
4836
          temp_reg = gen_reg_rtx (OImode);
4837
          if (unsignedp)
4838
              emit_insn(gen_zero_extendqioi2 (temp_reg, src));
4839
          else
4840
              emit_insn(gen_extendqioi2 (temp_reg, src));
4841
          riscv_emit_move(dest, gen_lowpart(QImode, temp_reg));
4842
          return true;
4843
        }
4844
        case HImode:
4845
        {
4846
          temp_reg = gen_reg_rtx (OImode);
4847
          if (unsignedp)
4848
              emit_insn(gen_zero_extendhioi2 (temp_reg, src));
4849
          else
4850
              emit_insn(gen_extendhioi2 (temp_reg, src));
4851
          riscv_emit_move(dest, gen_lowpart(HImode, temp_reg));
4852
          return true;
4853
        }
4854
        case SImode:
4855
        {
4856
          temp_reg = gen_reg_rtx (OImode);
4857
          if (unsignedp)
4858
              emit_insn(gen_zero_extendsioi2 (temp_reg, src));
4859
          else
4860
              emit_insn(gen_extendsioi2 (temp_reg, src));
4861
          riscv_emit_move(dest, gen_lowpart(SImode, temp_reg));
4862
          return true;
4863
        }
4864
        case DImode:
4865
        {
4866
          temp_reg = gen_reg_rtx (OImode);
4867
          if (unsignedp)
4868
              emit_insn(gen_zero_extenddioi2 (temp_reg, src));
4869
          else
4870
              emit_insn(gen_extenddioi2 (temp_reg, src));
4871
          riscv_emit_move(dest, gen_lowpart(SImode, temp_reg));
4872
          return true;
4873
        }
4874
      }
4875
    }
4876
    */
4877
  return false;
4878
  }
4879
}
4880
4752
/* Generate code to convert FROM to floating point
4881
/* Generate code to convert FROM to floating point
4753
   and store in TO.  FROM must be fixed point and not VOIDmode.
4882
   and store in TO.  FROM must be fixed point and not VOIDmode.
4754
   UNSIGNEDP nonzero means regard FROM as unsigned.
4883
   UNSIGNEDP nonzero means regard FROM as unsigned.
(-)a/riscv-gcc/gcc/optabs.h (+7 lines)
Lines 294-299 extern int have_sub2_insn (rtx, rtx); Link Here
294
   into X (with mode MTO).  Do zero-extension if UNSIGNEDP is nonzero.  */
294
   into X (with mode MTO).  Do zero-extension if UNSIGNEDP is nonzero.  */
295
extern rtx_insn *gen_extend_insn (rtx, rtx, machine_mode, machine_mode, int);
295
extern rtx_insn *gen_extend_insn (rtx, rtx, machine_mode, machine_mode, int);
296
296
297
/* Seperate (set (reg:QI target) (mem:QI (address))) 
298
    to
299
    (set (reg:DI temp) (zero_extend:DI (mem:DI (address))))
300
  (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
301
  with auto-sign extend */
302
extern bool gen_extend_insn_auto(machine_mode, machine_mode, rtx, rtx, int);
303
297
/* Generate code for a FLOAT_EXPR.  */
304
/* Generate code for a FLOAT_EXPR.  */
298
extern void expand_float (rtx, rtx, int);
305
extern void expand_float (rtx, rtx, int);
299
306

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