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(-)a/home/levy/Desktop/toolchain-original/riscv-gnu-toolchain/riscv-gcc/gcc/config/riscv/riscv.c (+11 lines)
Lines 1528-1533 riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) Link Here
1528
bool
1528
bool
1529
riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
1529
riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
1530
{
1530
{
1531
  
1532
  if (GET_MODE_CLASS (mode) == MODE_INT
1533
	      && GET_MODE_SIZE (mode) < UNITS_PER_WORD
1534
        && can_create_pseudo_p()
1535
        && MEM_P (src))
1536
  {
1537
    int extend = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND);
1538
    if(gen_extend_insn_auto(mode, word_mode, dest, src, extend))
1539
        return true;
1540
  }
1541
1531
  if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
1542
  if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
1532
    {
1543
    {
1533
      rtx reg;
1544
      rtx reg;
(-)a/home/levy/Desktop/toolchain-original/riscv-gnu-toolchain/riscv-gcc/gcc/optabs.c (-2 / +91 lines)
Lines 4737-4743 have_sub2_insn (rtx x, rtx y) Link Here
4737
4737
4738
  return 1;
4738
  return 1;
4739
}
4739
}
4740
4740
4741
/* Generate the body of an insn to extend Y (with mode MFROM)
4741
/* Generate the body of an insn to extend Y (with mode MFROM)
4742
   into X (with mode MTO).  Do zero-extension if UNSIGNEDP is nonzero.  */
4742
   into X (with mode MTO).  Do zero-extension if UNSIGNEDP is nonzero.  */
4743
4743
Lines 4748-4754 gen_extend_insn (rtx x, rtx y, machine_mode mto, Link Here
4748
  enum insn_code icode = can_extend_p (mto, mfrom, unsignedp);
4748
  enum insn_code icode = can_extend_p (mto, mfrom, unsignedp);
4749
  return GEN_FCN (icode) (x, y);
4749
  return GEN_FCN (icode) (x, y);
4750
}
4750
}
4751
4751
4752
4753
/* Seperate (set (reg:QI target) (mem:QI (address))) 
4754
    to
4755
    (set (reg:DI temp) (zero_extend:DI (mem:DI (address))))
4756
  (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
4757
  with auto-sign extend */
4758
4759
bool 
4760
gen_extend_insn_auto (machine_mode mode, 
4761
      machine_mode current_word_mode, rtx dest, rtx src, int unsignedp)
4762
{
4763
  rtx temp_reg;
4764
  switch(current_word_mode)
4765
  {
4766
    /* RV32 */
4767
    case SImode:
4768
    {
4769
      switch(mode)
4770
      {
4771
        case QImode:
4772
        {
4773
          temp_reg = gen_reg_rtx (DImode);
4774
          if (unsignedp)
4775
              emit_insn(gen_zero_extendqisi2 (temp_reg, src));
4776
          else
4777
              emit_insn(gen_extendqisi2 (temp_reg, src));
4778
          riscv_emit_move(dest, gen_lowpart(QImode, temp_reg));
4779
          return true;
4780
        }
4781
        case HImode:
4782
        {
4783
          temp_reg = gen_reg_rtx (DImode);
4784
          if (unsignedp)
4785
              emit_insn(gen_zero_extendhisi2 (temp_reg, src));
4786
          else
4787
              emit_insn(gen_extendhisi2 (temp_reg, src));
4788
          riscv_emit_move(dest, gen_lowpart(HImode, temp_reg));
4789
          return true;
4790
        }
4791
      }
4792
    }
4793
    /* RV64 */
4794
    case DImode:
4795
    {
4796
      switch(mode)
4797
      {
4798
        case QImode:
4799
        {
4800
          temp_reg = gen_reg_rtx (DImode);
4801
          if (unsignedp)
4802
              emit_insn(gen_zero_extendqidi2 (temp_reg, src));
4803
          else
4804
              emit_insn(gen_extendqidi2 (temp_reg, src));
4805
          riscv_emit_move(dest, gen_lowpart(QImode, temp_reg));
4806
          return true;
4807
        }
4808
        case HImode:
4809
        {
4810
          temp_reg = gen_reg_rtx (DImode);
4811
          if (unsignedp)
4812
              emit_insn(gen_zero_extendhidi2 (temp_reg, src));
4813
          else
4814
              emit_insn(gen_extendhidi2 (temp_reg, src));
4815
          riscv_emit_move(dest, gen_lowpart(HImode, temp_reg));
4816
          return true;
4817
        }
4818
        case SImode:
4819
        {
4820
          temp_reg = gen_reg_rtx (DImode);
4821
          if (unsignedp)
4822
              emit_insn(gen_zero_extendsidi2 (temp_reg, src));
4823
          else
4824
              emit_insn(gen_extendsidi2 (temp_reg, src));
4825
          riscv_emit_move(dest, gen_lowpart(SImode, temp_reg));
4826
          return true;
4827
        }
4828
      }
4829
    }
4830
    /* RV128
4831
    case:OImode
4832
    {
4833
4834
    }
4835
    */
4836
  return false;
4837
  }
4838
}
4839
4840
4752
/* Generate code to convert FROM to floating point
4841
/* Generate code to convert FROM to floating point
4753
   and store in TO.  FROM must be fixed point and not VOIDmode.
4842
   and store in TO.  FROM must be fixed point and not VOIDmode.
4754
   UNSIGNEDP nonzero means regard FROM as unsigned.
4843
   UNSIGNEDP nonzero means regard FROM as unsigned.
(-)a/home/levy/Desktop/toolchain-original/riscv-gnu-toolchain/riscv-gcc/gcc/optabs.h (+7 lines)
Lines 294-299 extern int have_sub2_insn (rtx, rtx); Link Here
294
   into X (with mode MTO).  Do zero-extension if UNSIGNEDP is nonzero.  */
294
   into X (with mode MTO).  Do zero-extension if UNSIGNEDP is nonzero.  */
295
extern rtx_insn *gen_extend_insn (rtx, rtx, machine_mode, machine_mode, int);
295
extern rtx_insn *gen_extend_insn (rtx, rtx, machine_mode, machine_mode, int);
296
296
297
/* Seperate (set (reg:QI target) (mem:QI (address))) 
298
    to
299
    (set (reg:DI temp) (zero_extend:DI (mem:DI (address))))
300
  (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
301
  with auto-sign extend */
302
extern bool gen_extend_insn_auto(machine_mode, machine_mode, rtx, rtx, int);
303
297
/* Generate code for a FLOAT_EXPR.  */
304
/* Generate code for a FLOAT_EXPR.  */
298
extern void expand_float (rtx, rtx, int);
305
extern void expand_float (rtx, rtx, int);
299
306

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