Index: alpha.c
===================================================================
RCS file: /cvsroot/gcc/gcc/gcc/config/alpha/alpha.c,v
retrieving revision 1.332
diff -u -p -r1.332 alpha.c
--- alpha.c	11 Oct 2003 16:54:16 -0000	1.332
+++ alpha.c	17 Oct 2003 20:41:44 -0000
@@ -3150,33 +3150,15 @@ alpha_emit_conditional_branch (enum rtx_
     {
       cmp_mode = DImode;
 
-      /* The following optimizations are only for signed compares.  */
-      if (code != LEU && code != LTU && code != GEU && code != GTU)
-	{
-	  /* Whee.  Compare and branch against 0 directly.  */
-	  if (op1 == const0_rtx)
-	    cmp_code = NIL, branch_code = code;
-
-	  /* We want to use cmpcc/bcc when we can, since there is a zero delay
-	     bypass between logicals and br/cmov on EV5.  But we don't want to
-	     force valid immediate constants into registers needlessly.  */
-	  else if (GET_CODE (op1) == CONST_INT)
-	    {
-	      HOST_WIDE_INT v = INTVAL (op1), n = -v;
-
-	      if (! CONST_OK_FOR_LETTER_P (v, 'I')
-		  && (CONST_OK_FOR_LETTER_P (n, 'K')
-		      || CONST_OK_FOR_LETTER_P (n, 'L')))
-		{
-		  cmp_code = PLUS, branch_code = code;
-		  op1 = GEN_INT (n);
-		}
-	    }
-	}
+      /* For signed compares, we can compare and branch against 0
+	 directly.  */
+      if (op1 == const0_rtx
+	  && code != LEU && code != LTU && code != GEU && code != GTU)
+	cmp_code = NIL, branch_code = code;
 
       if (!reg_or_0_operand (op0, DImode))
 	op0 = force_reg (DImode, op0);
-      if (cmp_code != PLUS && !reg_or_8bit_operand (op1, DImode))
+      if (!reg_or_8bit_operand (op1, DImode))
 	op1 = force_reg (DImode, op1);
     }