Attachment #43068 for bug #83565

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{
  unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
  unsigned HOST_WIDE_INT inner_nz;
  enum rtx_code code = GET_CODE (x);
  machine_mode inner_mode;
  unsigned int inner_width;
  scalar_int_mode xmode;

    return nonzero;

  /* If MODE is wider than X, but both are a single word for both the host
     and target machines, we can compute this from which bits of the object
     might be nonzero in its own mode, taking into account the fact that, on
     CISC machines, accessing an object in a wider mode generally causes the
     high-order bits to become undefined, so they are not known to be zero.
     We extend this reasoning to RISC machines for rotate operations since the
     semantics of the operations in the larger mode is not well defined.  */
  if (mode_width > xmode_width
      && mode_width > xmode_width
      && xmode_width <= BITS_PER_WORD
      && xmode_width <= HOST_BITS_PER_WIDE_INT
      && (!WORD_REGISTER_OPERATIONS || code == ROTATE || code == ROTATERT))
    {
      nonzero &= cached_nonzero_bits (x, xmode,
				      known_x, known_mode, known_ret);


  /* Please keep nonzero_bits_binary_arith_p above in sync with
     the code in the switch below.  */
  code = GET_CODE (x);
  switch (code)
    {
    case REG:

	}
      break;

    case ASHIFT:
    case ASHIFTRT:
    case LSHIFTRT:
    case ASHIFT:
    case ROTATE:
    case ROTATERT:
      /* The nonzero bits are in two classes: any bits within MODE
	 that aren't in xmode are always significant.  The rest of the
	 nonzero bits are those that are significant in the operand of

	  if (mode_width > xmode_width)
	    outer = (op_nonzero & nonzero & ~mode_mask);

	  switch (code)
	    inner >>= count;
	  else if (code == ASHIFTRT)
	    {
	    case ASHIFT:
	      inner <<= count;
	      break;

	    case LSHIFTRT:
	      inner >>= count;
	      break;

	    case ASHIFTRT:
	      inner >>= count;

	      /* If the sign bit may have been nonzero before the shift, we

	      if (inner & (HOST_WIDE_INT_1U << (xmode_width - 1 - count)))
		inner |= (((HOST_WIDE_INT_1U << count) - 1)
			  << (xmode_width - count));
	      break;

	    case ROTATE:
	      inner = (inner << (count % xmode_width)
		       | (inner >> (xmode_width - (count % xmode_width))))
		      & mode_mask;
	      break;

	    case ROTATERT:
	      inner = (inner >> (count % xmode_width)
		       | (inner << (xmode_width - (count % xmode_width))))
		      & mode_mask;
	      break;

	    default:
	      gcc_unreachable ();
	    }
	  else if (code == ASHIFT)
	    inner <<= count;
	  else
	    inner = ((inner << (count % xmode_width)
		      | (inner >> (xmode_width - (count % xmode_width))))
		     & mode_mask);

	  nonzero &= (outer | inner);
	}

Return to bug 83565

Lines 4429-4435 nonzero_bits1 (const_rtx x, scalar_int_m Link Here

(-)rtlanal.c (-21 / +38 lines)
4429	{	4429	{
4430	unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);	4430	unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
4431	unsigned HOST_WIDE_INT inner_nz;	4431	unsigned HOST_WIDE_INT inner_nz;
4432	enum rtx_code code;	4432	enum rtx_code code = GET_CODE (x);
4433	machine_mode inner_mode;	4433	machine_mode inner_mode;
4434	unsigned int inner_width;	4434	unsigned int inner_width;
4435	scalar_int_mode xmode;	4435	scalar_int_mode xmode;
Lines 4465-4480 nonzero_bits1 (const_rtx x, scalar_int_m Link Here
4465	return nonzero;	4465	return nonzero;
4466		4466
4467	/* If MODE is wider than X, but both are a single word for both the host	4467	/* If MODE is wider than X, but both are a single word for both the host
4468	and target machines, we can compute this from which bits of the	4468	and target machines, we can compute this from which bits of the object
4469	object might be nonzero in its own mode, taking into account the fact	4469	might be nonzero in its own mode, taking into account the fact that, on
4470	that on many CISC machines, accessing an object in a wider mode	4470	CISC machines, accessing an object in a wider mode generally causes the
4471	causes the high-order bits to become undefined. So they are	4471	high-order bits to become undefined, so they are not known to be zero.
4472	not known to be zero. */	4472	We extend this reasoning to RISC machines for rotate operations since the
4473		4473	semantics of the operations in the larger mode is not well defined. */
4474	if (!WORD_REGISTER_OPERATIONS	4474	if (mode_width > xmode_width
4475	&& mode_width > xmode_width
4476	&& xmode_width <= BITS_PER_WORD	4475	&& xmode_width <= BITS_PER_WORD
4477	&& xmode_width <= HOST_BITS_PER_WIDE_INT)	4476	&& xmode_width <= HOST_BITS_PER_WIDE_INT
		4477	&& (!WORD_REGISTER_OPERATIONS \|\| code == ROTATE \|\| code == ROTATERT))
4478	{	4478	{
4479	nonzero &= cached_nonzero_bits (x, xmode,	4479	nonzero &= cached_nonzero_bits (x, xmode,
4480	known_x, known_mode, known_ret);	4480	known_x, known_mode, known_ret);
Lines 4484-4490 nonzero_bits1 (const_rtx x, scalar_int_m Link Here
4484		4484
4485	/* Please keep nonzero_bits_binary_arith_p above in sync with	4485	/* Please keep nonzero_bits_binary_arith_p above in sync with
4486	the code in the switch below. */	4486	the code in the switch below. */
4487	code = GET_CODE (x);
4488	switch (code)	4487	switch (code)
4489	{	4488	{
4490	case REG:	4489	case REG:
Lines 4760-4769 nonzero_bits1 (const_rtx x, scalar_int_m Link Here
4760	}	4759	}
4761	break;	4760	break;
4762		4761
		4762	case ASHIFT:
4763	case ASHIFTRT:	4763	case ASHIFTRT:
4764	case LSHIFTRT:	4764	case LSHIFTRT:
4765	case ASHIFT:
4766	case ROTATE:	4765	case ROTATE:
		4766	case ROTATERT:
4767	/* The nonzero bits are in two classes: any bits within MODE	4767	/* The nonzero bits are in two classes: any bits within MODE
4768	that aren't in xmode are always significant. The rest of the	4768	that aren't in xmode are always significant. The rest of the
4769	nonzero bits are those that are significant in the operand of	4769	nonzero bits are those that are significant in the operand of
Lines 4786-4795 nonzero_bits1 (const_rtx x, scalar_int_m Link Here
4786	if (mode_width > xmode_width)	4786	if (mode_width > xmode_width)
4787	outer = (op_nonzero & nonzero & ~mode_mask);	4787	outer = (op_nonzero & nonzero & ~mode_mask);
4788		4788
4789	if (code == LSHIFTRT)	4789	switch (code)
4790	inner >>= count;
4791	else if (code == ASHIFTRT)
4792	{	4790	{
		4791	case ASHIFT:
		4792	inner <<= count;
		4793	break;
		4794
		4795	case LSHIFTRT:
		4796	inner >>= count;
		4797	break;
		4798
		4799	case ASHIFTRT:
4793	inner >>= count;	4800	inner >>= count;
4794		4801
4795	/* If the sign bit may have been nonzero before the shift, we	4802	/* If the sign bit may have been nonzero before the shift, we
Lines 4798-4810 nonzero_bits1 (const_rtx x, scalar_int_m Link Here
4798	if (inner & (HOST_WIDE_INT_1U << (xmode_width - 1 - count)))	4805	if (inner & (HOST_WIDE_INT_1U << (xmode_width - 1 - count)))
4799	inner \|= (((HOST_WIDE_INT_1U << count) - 1)	4806	inner \|= (((HOST_WIDE_INT_1U << count) - 1)
4800	<< (xmode_width - count));	4807	<< (xmode_width - count));
		4808	break;
		4809
		4810	case ROTATE:
		4811	inner = (inner << (count % xmode_width)
		4812	\| (inner >> (xmode_width - (count % xmode_width))))
		4813	& mode_mask;
		4814	break;
		4815
		4816	case ROTATERT:
		4817	inner = (inner >> (count % xmode_width)
		4818	\| (inner << (xmode_width - (count % xmode_width))))
		4819	& mode_mask;
		4820	break;
		4821
		4822	default:
		4823	gcc_unreachable ();
4801	}	4824	}
4802	else if (code == ASHIFT)
4803	inner <<= count;
4804	else
4805	inner = ((inner << (count % xmode_width)
4806	\| (inner >> (xmode_width - (count % xmode_width))))
4807	& mode_mask);
4808		4825
4809	nonzero &= (outer \| inner);	4826	nonzero &= (outer \| inner);
4810	}	4827	}