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(-)gcc/config/rs6000/rs6000.md (-6 / +8 lines)
Lines 5387-5396 (define_insn "*friz" Link Here
5387
   xsrdpiz %x0,%x1"
5387
   xsrdpiz %x0,%x1"
5388
  [(set_attr "type" "fp")])
5388
  [(set_attr "type" "fp")])
5389
5389
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;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
5390
;; Opitmize converting SF/DFmode to signed SImode and back to SF/DFmode.  This
5391
;; load to properly sign extend the value, but at least doing a store, load
5391
;; optimization prevents on ISA 2.06 systems and earlier having to store the
5392
;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
5392
;; value from the FPR/vector unit to the stack, load the value into a GPR, sign
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;; if we have 32-bit memory ops
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;; extend it, store it back on the stack from the GPR, load it back into the
5394
;; FP/vector unit to do the rounding. If we have direct move (ISA 2.07),
5395
;; disable using store and load to sign/zero extend the value.
5394
(define_insn_and_split "*round32<mode>2_fprs"
5396
(define_insn_and_split "*round32<mode>2_fprs"
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  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5397
  [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5396
	(float:SFDF
5398
	(float:SFDF
Lines 5399-5405 (define_insn_and_split "*round32<mode>2_ Link Here
5399
   (clobber (match_scratch:DI 3 "=d"))]
5401
   (clobber (match_scratch:DI 3 "=d"))]
5400
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5402
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5401
   && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
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   && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
5402
   && can_create_pseudo_p ()"
5404
   && !TARGET_DIRECT_MOVE && can_create_pseudo_p ()"
5403
  "#"
5405
  "#"
5404
  ""
5406
  ""
5405
  [(pc)]
5407
  [(pc)]
Lines 5431-5437 (define_insn_and_split "*roundu32<mode>2 Link Here
5431
   (clobber (match_scratch:DI 2 "=d"))
5433
   (clobber (match_scratch:DI 2 "=d"))
5432
   (clobber (match_scratch:DI 3 "=d"))]
5434
   (clobber (match_scratch:DI 3 "=d"))]
5433
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5435
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5434
   && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
5436
   && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU && !TARGET_DIRECT_MOVE
5435
   && can_create_pseudo_p ()"
5437
   && can_create_pseudo_p ()"
5436
  "#"
5438
  "#"
5437
  ""
5439
  ""
(-)gcc/testsuite/gcc.target/powerpc/ppc-round2.c (+42 lines)
Line 0 Link Here
1
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
2
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
3
/* { dg-require-effective-target powerpc_p8vector_ok } */
4
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
5
/* { dg-options "-O2 -mcpu=power8" } */
6
/* { dg-final { scan-assembler-times "fcfid "      2 } } */
7
/* { dg-final { scan-assembler-times "fcfids "     2 } } */
8
/* { dg-final { scan-assembler-times "fctiwuz "    2 } } */
9
/* { dg-final { scan-assembler-times "fctiwz "     2 } } */
10
/* { dg-final { scan-assembler-times "mfvsrd "     4 } } */
11
/* { dg-final { scan-assembler-times "mtvsrwa "    2 } } */
12
/* { dg-final { scan-assembler-times "mtvsrwz "    2 } } */
13
/* { dg-final { scan-assembler-not   "lwz"           } } */
14
/* { dg-final { scan-assembler-not   "lfiwax "       } } */
15
/* { dg-final { scan-assembler-not   "lfiwzx "       } } */
16
/* { dg-final { scan-assembler-not   "stw"           } } */
17
/* { dg-final { scan-assembler-not   "stfiwx "       } } */
18
19
/* Make sure we don't have loads/stores to the GPR unit.  */
20
double
21
round_double_int (double a)
22
{
23
  return (double)(int)a;
24
}
25
26
float
27
round_float_int (float a)
28
{
29
  return (float)(int)a;
30
}
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32
double
33
round_double_uint (double a)
34
{
35
  return (double)(unsigned int)a;
36
}
37
38
float
39
round_float_uint (float a)
40
{
41
  return (float)(unsigned int)a;
42
}

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