Lines 8344-8378
(define_expand "extenddftf2"
Link Here
|
8344 |
{ |
8344 |
{ |
8345 |
if (TARGET_E500_DOUBLE) |
8345 |
if (TARGET_E500_DOUBLE) |
8346 |
emit_insn (gen_spe_extenddftf2 (operands[0], operands[1])); |
8346 |
emit_insn (gen_spe_extenddftf2 (operands[0], operands[1])); |
|
|
8347 |
else if (TARGET_VSX) |
8348 |
emit_insn (gen_extenddftf2_vsx (operands[0], operands[1], |
8349 |
CONST0_RTX (DFmode))); |
8347 |
else |
8350 |
else |
8348 |
emit_insn (gen_extenddftf2_fprs (operands[0], operands[1])); |
8351 |
{ |
|
|
8352 |
rtx tmp = gen_reg_rtx (DFmode); |
8353 |
rs6000_emit_move (tmp, CONST0_RTX (DFmode), DFmode); |
8354 |
emit_insn (gen_extenddftf2_nonvsx (operands[0], operands[1], tmp)); |
8355 |
} |
8349 |
DONE; |
8356 |
DONE; |
8350 |
}) |
8357 |
}) |
8351 |
|
8358 |
|
8352 |
(define_expand "extenddftf2_fprs" |
8359 |
(define_insn_and_split "extenddftf2_nonvsx" |
8353 |
[(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") |
8360 |
[(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r") |
8354 |
(float_extend:TF (match_operand:DF 1 "input_operand" ""))) |
8361 |
(float_extend:TF (match_operand:DF 1 "input_operand" "d,r,m,d,r"))) |
8355 |
(use (match_dup 2))])] |
8362 |
(use (match_operand:DF 2 "gpc_reg_operand" "d,r,d,d,r"))] |
8356 |
"!TARGET_IEEEQUAD |
8363 |
"!TARGET_IEEEQUAD && !TARGET_VSX |
8357 |
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT |
8364 |
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT |
8358 |
&& TARGET_LONG_DOUBLE_128" |
8365 |
&& TARGET_LONG_DOUBLE_128" |
|
|
8366 |
"#" |
8367 |
"&& reload_completed" |
8368 |
[(pc)] |
8359 |
{ |
8369 |
{ |
8360 |
/* VSX can create 0.0 directly, otherwise let rs6000_emit_move create |
8370 |
const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0; |
8361 |
the proper constant. */ |
8371 |
const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode); |
8362 |
if (TARGET_VSX) |
8372 |
emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word), |
8363 |
operands[2] = CONST0_RTX (DFmode); |
8373 |
operands[1]); |
8364 |
else |
8374 |
emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word), |
8365 |
{ |
8375 |
operands[2]); |
8366 |
operands[2] = gen_reg_rtx (DFmode); |
8376 |
DONE; |
8367 |
rs6000_emit_move (operands[2], CONST0_RTX (DFmode), DFmode); |
|
|
8368 |
} |
8369 |
}) |
8377 |
}) |
8370 |
|
8378 |
|
8371 |
(define_insn_and_split "*extenddftf2_internal" |
8379 |
(define_insn_and_split "extenddftf2_vsx" |
8372 |
[(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,ws,d,&d,r") |
8380 |
[(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,d,r,r") |
8373 |
(float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,md,rm"))) |
8381 |
(float_extend:TF (match_operand:DF 1 "input_operand" "d,r,m,ws,Y,r"))) |
8374 |
(use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,j,m,d,n"))] |
8382 |
(use (match_operand:DF 2 "zero_fp_constant" "j,j,j,j,j,j"))] |
8375 |
"!TARGET_IEEEQUAD |
8383 |
"!TARGET_IEEEQUAD && TARGET_VSX |
8376 |
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT |
8384 |
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT |
8377 |
&& TARGET_LONG_DOUBLE_128" |
8385 |
&& TARGET_LONG_DOUBLE_128" |
8378 |
"#" |
8386 |
"#" |