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(-)a/gcc/config/arm/arm.c (+28 lines)
Lines 30212-30217 arm_conditional_register_usage (void) Link Here
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      for (regno = FIRST_HI_REGNUM;
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      for (regno = FIRST_HI_REGNUM;
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	   regno <= LAST_HI_REGNUM; ++regno)
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	   regno <= LAST_HI_REGNUM; ++regno)
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	fixed_regs[regno] = call_used_regs[regno] = 1;
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	fixed_regs[regno] = call_used_regs[regno] = 1;
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      /* This is a temporary part fix for PR61578 (sequel to PR59535).
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	 The original reason why most high registers was taken out
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	 of the available registers list for -Os was because saving
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	 them (they're mostly callee-saved) is quite expensive, since
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	 high registers have to be copied to low registers first.
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	 Ideally we could use IP also when optimizing for size,
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	 since it's call-clobbered and there's thus no code cost
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	 to make it available.
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	 Though it has been shown that the register allocator generates
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	 smaller code when IP is not used. This might be indicating a more
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	 fundamental problem in the reload passes, but as a short-term
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	 expedient work-around it could be possible to exclude IP. At
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	 least this would make it possible to compare code sizes when
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	 trying to solve the root-problem.
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	 If using IP, then reload does need to be aware that once a value
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	 is in a high register, really spilling it to memory, or loading it
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	 from memory is an expensive operation, since such transfers have
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	 to go via a low register.  */
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      if (target_ip_fixed)
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	{
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	  /* Not using IP reg either. */
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	  fixed_regs[IP_REGNUM] = call_used_regs[IP_REGNUM] = 1;
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	}
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    }
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    }
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  /* The link register can be clobbered by any branch insn,
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  /* The link register can be clobbered by any branch insn,
(-)a/gcc/config/arm/arm.opt (+4 lines)
Lines 260-265 Target Report Var(fix_cm3_ldrd) Init(2) Link Here
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Avoid overlapping destination and address registers on LDRD instructions
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Avoid overlapping destination and address registers on LDRD instructions
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that may trigger Cortex-M3 errata.
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that may trigger Cortex-M3 errata.
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mip-fixed
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Target Report Var(target_ip_fixed) Init(1)
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Avoid using IP register when optimizing size for thumb1.
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munaligned-access
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munaligned-access
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Target Report Var(unaligned_access) Init(2)
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Target Report Var(unaligned_access) Init(2)
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Enable unaligned word and halfword accesses to packed data.
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Enable unaligned word and halfword accesses to packed data.
(-)a/gcc/doc/invoke.texi (+8 lines)
Lines 546-551 Objective-C and Objective-C++ Dialects}. Link Here
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-munaligned-access @gol
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-munaligned-access @gol
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-mneon-for-64bits @gol
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-mneon-for-64bits @gol
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-mslow-flash-data @gol
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-mslow-flash-data @gol
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-mip-fixed @gol
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-mrestrict-it}
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-mrestrict-it}
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@emph{AVR Options}
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@emph{AVR Options}
Lines 13010-13015 Therefore literal load is minimized for better performance. Link Here
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This option is only supported when compiling for ARMv7 M-profile and
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This option is only supported when compiling for ARMv7 M-profile and
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off by default.
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off by default.
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@item -mip-fixed
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@opindex mip-fixed
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When optimizing for size, the cost for using high registers on Thumb1
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is expensive. This option avoids using the IP high register by the
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register allocator. This option is only supported when compiling for
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Thumb1 and -Os and is on by default.
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@item -mrestrict-it
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@item -mrestrict-it
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@opindex mrestrict-it
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@opindex mrestrict-it
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Restricts generation of IT blocks to conform to the rules of ARMv8.
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Restricts generation of IT blocks to conform to the rules of ARMv8.

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