GCC Bugzilla – Attachment 26680 Details for
Bug 52278
[4.8/4.9/5 Regression] [avr] inefficient register allocation for SUBREGs
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add.c.198r.reload
add.c.198r.reload (text/plain), 6.60 KB, created by
Georg-Johann Lay
on 2012-02-16 14:06:43 UTC
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Description:
add.c.198r.reload
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Creator:
Georg-Johann Lay
Created:
2012-02-16 14:06:43 UTC
Size:
6.60 KB
patch
obsolete
> >;; Function add (add, funcdef_no=0, decl_uid=1318, cgraph_uid=0) > >insn=6, live_throughout: 32, dead_or_set: 24, 25, 45 >insn=19, live_throughout: 32, 45, dead_or_set: 24 >insn=20, live_throughout: 24, 32, dead_or_set: 25, 45 >insn=14, live_throughout: 24, 25, 32, dead_or_set: >changing reg in insn 6 >Spilling for insn 6. > >Reloads for insn # 6 >Reload 0: reload_in (HI) = (reg:HI 24 r24 [ val ]) > reload_out (HI) = (reg:HI 18 r18 [45]) > LD_REGS, RELOAD_OTHER (opnum = 0) > reload_in_reg: (reg:HI 24 r24 [ val ]) > reload_out_reg: (reg:HI 18 r18 [45]) > reload_reg_rtx: (reg:HI 18 r18 [45]) > > >try_optimize_cfg iteration 1 > >starting the processing of deferred insns >ending the processing of deferred insns >starting the processing of deferred insns >ending the processing of deferred insns >df_analyze called >df_worklist_dataflow_doublequeue:n_basic_blocks 3 n_edges 2 count 3 ( 1) >df_worklist_dataflow_doublequeue:n_basic_blocks 3 n_edges 2 count 3 ( 1) > > >add > >Dataflow summary: >;; invalidated by call 0 [r0] 1 [r1] 18 [r18] 19 [r19] 20 [r20] 21 [r21] 22 [r22] 23 [r23] 24 [r24] 25 [r25] 26 [r26] 27 [r27] 30 [r30] 31 [r31] 33 [__SP_H__] 35 [argH] >;; hardware regs used 32 [__SP_L__] >;; regular block artificial uses 32 [__SP_L__] >;; eh block artificial uses 32 [__SP_L__] 34 [argL] >;; entry block defs 8 [r8] 9 [r9] 10 [r10] 11 [r11] 12 [r12] 13 [r13] 14 [r14] 15 [r15] 16 [r16] 17 [r17] 18 [r18] 19 [r19] 20 [r20] 21 [r21] 22 [r22] 23 [r23] 24 [r24] 25 [r25] 32 [__SP_L__] >;; exit block uses 24 [r24] 25 [r25] 32 [__SP_L__] >;; regs ever live 18[r18] 19[r19] 24[r24] 25[r25] >;; ref usage r8={1d} r9={1d} r10={1d} r11={1d} r12={1d} r13={1d} r14={1d} r15={1d} r16={1d} r17={1d} r18={3d,2u} r19={3d,2u} r20={1d} r21={1d} r22={1d} r23={1d} r24={2d,3u} r25={2d,3u} r32={1d,2u} >;; total ref usage 37{25d,12u,0e} in 5{5 regular + 0 call} insns. >(note 1 0 4 NOTE_INSN_DELETED) > > >;; Basic block 2 , prev 0, next 1, loop_depth 0, count 0, freq 10000, maybe hot, flags: reachable rtl modified. >;; Predecessors: ENTRY [100.0%] (fallthru) >;; bb 2 artificial_defs: { } >;; bb 2 artificial_uses: { u-1(32){ }} >;; lr in 24 [r24] 25 [r25] 32 [__SP_L__] >;; lr use 24 [r24] 25 [r25] 32 [__SP_L__] >;; lr def 18 [r18] 19 [r19] 24 [r24] 25 [r25] >;; live in 24 [r24] 25 [r25] 32 [__SP_L__] >;; live gen 18 [r18] 19 [r19] 24 [r24] 25 [r25] >;; live kill > >(note 4 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK) > >(note 2 4 3 2 NOTE_INSN_DELETED) > >(note 3 2 23 2 NOTE_INSN_FUNCTION_BEG) > >(insn 23 3 6 2 (set (reg:HI 18 r18 [45]) > (reg:HI 24 r24 [ val ])) add.c:4 22 {*movhi} > (nil)) > >(insn 6 23 19 2 (parallel [ > (set (reg:HI 18 r18 [45]) > (plus:HI (reg:HI 18 r18 [45]) > (const_int 1 [0x1]))) > (clobber (scratch:QI)) > ]) add.c:4 42 {addhi3_clobber} > (nil)) > >(insn 19 6 20 2 (set (reg:QI 24 r24) > (reg:QI 18 r18 [45])) add.c:5 18 {movqi_insn} > (nil)) > >(insn 20 19 14 2 (set (reg:QI 25 r25 [+1 ]) > (reg:QI 19 r19 [+1 ])) add.c:5 18 {movqi_insn} > (nil)) > >(insn 14 20 21 2 (use (reg/i:HI 24 r24)) add.c:5 -1 > (nil)) > >;; Successors: EXIT [100.0%] (fallthru) >;; lr out 24 [r24] 25 [r25] 32 [__SP_L__] >;; live out 24 [r24] 25 [r25] 32 [__SP_L__] > > >(note 21 14 0 NOTE_INSN_DELETED) > > >;; Function sext_hi (sext_hi, funcdef_no=1, decl_uid=1321, cgraph_uid=1) > >insn=2, live_throughout: 32, dead_or_set: 24, 25, 44 >insn=6, live_throughout: 32, dead_or_set: 44, 45 >insn=21, live_throughout: 32, 45, dead_or_set: 22 >insn=22, live_throughout: 22, 32, 45, dead_or_set: 23 >insn=23, live_throughout: 22, 23, 32, 45, dead_or_set: 24 >insn=24, live_throughout: 22, 23, 24, 32, dead_or_set: 25, 45 >insn=14, live_throughout: 22, 23, 24, 25, 32, dead_or_set: >changing reg in insn 2 >changing reg in insn 6 >changing reg in insn 6 >deleting insn with uid = 2. > > >try_optimize_cfg iteration 1 > >starting the processing of deferred insns >ending the processing of deferred insns >starting the processing of deferred insns >ending the processing of deferred insns >df_analyze called >df_worklist_dataflow_doublequeue:n_basic_blocks 3 n_edges 2 count 3 ( 1) >df_worklist_dataflow_doublequeue:n_basic_blocks 3 n_edges 2 count 3 ( 1) > > >sext_hi > >Dataflow summary: >;; invalidated by call 0 [r0] 1 [r1] 18 [r18] 19 [r19] 20 [r20] 21 [r21] 22 [r22] 23 [r23] 24 [r24] 25 [r25] 26 [r26] 27 [r27] 30 [r30] 31 [r31] 33 [__SP_H__] 35 [argH] >;; hardware regs used 32 [__SP_L__] >;; regular block artificial uses 32 [__SP_L__] >;; eh block artificial uses 32 [__SP_L__] 34 [argL] >;; entry block defs 8 [r8] 9 [r9] 10 [r10] 11 [r11] 12 [r12] 13 [r13] 14 [r14] 15 [r15] 16 [r16] 17 [r17] 18 [r18] 19 [r19] 20 [r20] 21 [r21] 22 [r22] 23 [r23] 24 [r24] 25 [r25] 32 [__SP_L__] >;; exit block uses 22 [r22] 23 [r23] 24 [r24] 25 [r25] 32 [__SP_L__] >;; regs ever live 16[r16] 17[r17] 18[r18] 19[r19] 22[r22] 23[r23] 24[r24] 25[r25] >;; ref usage r8={1d} r9={1d} r10={1d} r11={1d} r12={1d} r13={1d} r14={1d} r15={1d} r16={2d,1u} r17={2d,1u} r18={2d,1u} r19={2d,1u} r20={1d} r21={1d} r22={2d,2u} r23={2d,2u} r24={2d,3u} r25={2d,3u} r32={1d,2u} >;; total ref usage 43{27d,16u,0e} in 6{6 regular + 0 call} insns. >(note 1 0 4 NOTE_INSN_DELETED) > > >;; Basic block 2 , prev 0, next 1, loop_depth 0, count 0, freq 10000, maybe hot, flags: reachable rtl modified. >;; Predecessors: ENTRY [100.0%] (fallthru) >;; bb 2 artificial_defs: { } >;; bb 2 artificial_uses: { u-1(32){ }} >;; lr in 24 [r24] 25 [r25] 32 [__SP_L__] >;; lr use 24 [r24] 25 [r25] 32 [__SP_L__] >;; lr def 16 [r16] 17 [r17] 18 [r18] 19 [r19] 22 [r22] 23 [r23] 24 [r24] 25 [r25] >;; live in 24 [r24] 25 [r25] 32 [__SP_L__] >;; live gen 16 [r16] 17 [r17] 18 [r18] 19 [r19] 22 [r22] 23 [r23] 24 [r24] 25 [r25] >;; live kill > >(note 4 1 3 2 [bb 2] NOTE_INSN_BASIC_BLOCK) > >(note 3 4 6 2 NOTE_INSN_FUNCTION_BEG) > >(insn 6 3 21 2 (set (reg:SI 16 r16 [orig:45 val ] [45]) > (sign_extend:SI (reg/v:HI 24 r24 [orig:44 val ] [44]))) add.c:11 227 {extendhisi2} > (nil)) > >(insn 21 6 22 2 (set (reg:QI 22 r22) > (reg:QI 16 r16 [orig:45 val ] [45])) add.c:12 18 {movqi_insn} > (nil)) > >(insn 22 21 23 2 (set (reg:QI 23 r23 [+1 ]) > (reg:QI 17 r17 [ val+1 ])) add.c:12 18 {movqi_insn} > (nil)) > >(insn 23 22 24 2 (set (reg:QI 24 r24 [+2 ]) > (reg:QI 18 r18 [ val+2 ])) add.c:12 18 {movqi_insn} > (nil)) > >(insn 24 23 14 2 (set (reg:QI 25 r25 [+3 ]) > (reg:QI 19 r19 [ val+3 ])) add.c:12 18 {movqi_insn} > (nil)) > >(insn 14 24 25 2 (use (reg/i:SI 22 r22)) add.c:12 -1 > (nil)) > >;; Successors: EXIT [100.0%] (fallthru) >;; lr out 22 [r22] 23 [r23] 24 [r24] 25 [r25] 32 [__SP_L__] >;; live out 22 [r22] 23 [r23] 24 [r24] 25 [r25] 32 [__SP_L__] > > >(note 25 14 0 NOTE_INSN_DELETED) >
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