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(-)config/avr/predicates.md (+11 lines)
Lines 62-67 (define_predicate "const0_operand" Link Here
62
  (and (match_code "const_int,const_double")
62
  (and (match_code "const_int,const_double")
63
       (match_test "op == CONST0_RTX (mode)")))
63
       (match_test "op == CONST0_RTX (mode)")))
64
64
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;; Return 1 if OP is the one constant integer for MODE.
66
(define_predicate "const1_operand"
67
  (and (match_code "const_int")
68
       (match_test "op == CONST1_RTX (mode)")))
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70
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;; Return 1 if OP is constant integer 0..7 for MODE.
72
(define_predicate "const_0_to_7_operand"
73
  (and (match_code "const_int")
74
       (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
75
65
;; Returns true if OP is either the constant zero or a register.
76
;; Returns true if OP is either the constant zero or a register.
66
(define_predicate "reg_or_0_operand"
77
(define_predicate "reg_or_0_operand"
67
  (ior (match_operand 0 "register_operand")
78
  (ior (match_operand 0 "register_operand")
(-)config/avr/avr.md (+113 lines)
Lines 3390-3395 (define_insn "fmulsu" Link Here
3390
   (set_attr "cc" "clobber")])
3390
   (set_attr "cc" "clobber")])
3391
3391
3392
3392
3393
;; Some combiner patterns dealing with bits.
3394
;; See PR42210
3395
3396
;; Move bit $3.$4 into bit $0.$4
3397
(define_insn "*movbitqi.1-6.a"
3398
  [(set (match_operand:QI 0 "register_operand"                               "=r")
3399
        (ior:QI (and:QI (match_operand:QI 1 "register_operand"                "0")
3400
                        (match_operand:QI 2 "single_zero_operand"             "n"))
3401
                (and:QI (ashift:QI (match_operand:QI 3 "register_operand"     "r")
3402
                                   (match_operand:QI 4 "const_0_to_7_operand" "n"))
3403
                        (match_operand:QI 5 "single_one_operand"              "n"))))]
3404
  "INTVAL(operands[4]) == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))
3405
   && INTVAL(operands[4]) == exact_log2 (INTVAL(operands[5]) & GET_MODE_MASK (QImode))"
3406
  "bst %3,0\;bld %0,%4"
3407
  [(set_attr "length" "2")
3408
   (set_attr "cc" "none")])
3409
3410
;; Move bit $3.0 into bit $0.$4
3411
;; Variation of above. Unfortunately, there is no canonicalized representation
3412
;; of moving around bits.  So what we see here depends on how user writes down
3413
;; bit manipulations.
3414
(define_insn "*movbitqi.1-6.b"
3415
  [(set (match_operand:QI 0 "register_operand"                            "=r")
3416
        (ior:QI (and:QI (match_operand:QI 1 "register_operand"             "0")
3417
                        (match_operand:QI 2 "single_zero_operand"          "n"))
3418
                (ashift:QI (and:QI (match_operand:QI 3 "register_operand"  "r")
3419
                                   (const_int 1))
3420
                           (match_operand:QI 4 "const_0_to_7_operand"      "n"))))]
3421
  "INTVAL(operands[4]) == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))"
3422
  "bst %3,0\;bld %0,%4"
3423
  [(set_attr "length" "2")
3424
   (set_attr "cc" "none")])
3425
3426
;; Move bit $3.0 into bit $0.0.
3427
;; For bit 0, combiner generates slightly different pattern.
3428
(define_insn "*movbitqi.0"
3429
  [(set (match_operand:QI 0 "register_operand"                     "=r")
3430
        (ior:QI (and:QI (match_operand:QI 1 "register_operand"      "0")
3431
                        (match_operand:QI 2 "single_zero_operand"   "n"))
3432
                (and:QI (match_operand:QI 3 "register_operand"      "r")
3433
                        (const_int 1))))]
3434
  "0 == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))"
3435
  "bst %3,0\;bld %0,0"
3436
  [(set_attr "length" "2")
3437
   (set_attr "cc" "none")])
3438
3439
;; Move bit $2.0 into bit $0.7.
3440
;; For bit 7, combiner generates slightly different pattern
3441
(define_insn "*movbitqi.7"
3442
  [(set (match_operand:QI 0 "register_operand"                      "=r")
3443
        (ior:QI (and:QI (match_operand:QI 1 "register_operand"       "0")
3444
                        (const_int 127))
3445
                (ashift:QI (match_operand:QI 2 "register_operand"    "r")
3446
                           (const_int 7))))]
3447
  ""
3448
  "bst %2,0\;bld %0,7"
3449
  [(set_attr "length" "2")
3450
   (set_attr "cc" "none")])
3451
3452
;; Combiner transforms above four pattern into ZERO_EXTRACT if it sees MEM
3453
;; and input/output match.  We provide a special pattern for this, because
3454
;; in contrast to a IN/BST/BLD/OUT sequence we need less registers and the
3455
;; operation on I/O is atomic.
3456
(define_insn "*insv.io"
3457
  [(set (zero_extract:QI (mem:QI (match_operand 0 "low_io_address_operand" "n,n,n"))
3458
                         (const_int 1)
3459
                         (match_operand:QI 1 "const_0_to_7_operand"        "n,n,n"))
3460
        (match_operand:QI 2 "nonmemory_operand"                            "L,P,r"))]
3461
  ""
3462
  "@
3463
	cbi %m0-0x20,%1
3464
	sbi %m0-0x20,%1
3465
	sbrc %2,0\;sbi %m0-0x20,%1\;sbrs %2,0\;cbi %m0-0x20,%1"
3466
  [(set_attr "length" "1,1,4")
3467
   (set_attr "cc" "none")])
3468
3469
(define_insn "*insv.not.io"
3470
  [(set (zero_extract:QI (mem:QI (match_operand 0 "low_io_address_operand" "n"))
3471
                         (const_int 1)
3472
                         (match_operand:QI 1 "const_0_to_7_operand"        "n"))
3473
        (not:QI (match_operand:QI 2 "register_operand"                     "r")))]
3474
  ""
3475
  "sbrs %2,0\;sbi %m0-0x20,%1\;sbrc %2,0\;cbi %m0-0x20,%1"
3476
  [(set_attr "length" "4")
3477
   (set_attr "cc" "none")])
3478
3479
;; The insv expander.
3480
;; We only support 1-bit inserts
3481
(define_expand "insv"
3482
  [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "")
3483
                         (match_operand:QI 1 "const1_operand" "")        ; width
3484
                         (match_operand:QI 2 "const_0_to_7_operand" "")) ; pos
3485
        (match_operand:QI 3 "nonmemory_operand" ""))]
3486
  "optimize"
3487
  "")
3488
3489
;; Insert bit $2.0 into $0.$1
3490
(define_insn "*insv.reg"
3491
  [(set (zero_extract:QI (match_operand:QI 0 "register_operand"    "+r,d,d,l,l")
3492
                         (const_int 1)
3493
                         (match_operand:QI 1 "const_0_to_7_operand" "n,n,n,n,n"))
3494
        (match_operand:QI 2 "nonmemory_operand"                     "r,L,P,L,P"))]
3495
  ""
3496
  "@
3497
	bst %2,0\;bld %0,%1
3498
	andi %0,lo8(~(1<<%1))
3499
	ori %0,lo8(1<<%1)
3500
	clt\;bld %0,%1
3501
	set\;bld %0,%1"
3502
  [(set_attr "length" "2,1,1,2,2")
3503
   (set_attr "cc" "none,set_zn,set_zn,none,none")])
3504
3505
3393
;; Some combine patterns that try to fix bad code when a value is composed
3506
;; Some combine patterns that try to fix bad code when a value is composed
3394
;; from byte parts like in PR27663.
3507
;; from byte parts like in PR27663.
3395
;; The patterns give some release but the code still is not optimal,
3508
;; The patterns give some release but the code still is not optimal,

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