[forwarded from http://bugs.debian.org/197099] 3.3 release: $ gcc -pedantic -g -O2 -c stage-4.i stage-4.c: In function `scheduler_4': stage-4.c:1310: internal compiler error: in change_address_1, at emit-rtl.c:2017 Please submit a full bug report, with preprocessed source if appropriate. See <URL:http://gcc.gnu.org/bugs.html> for instructions. 3.4 CVS 20030531: $ gcc -pedantic -g -O2 -c stage-4.i stage-4.c: In function `scheduler_4': stage-4.c:1310: internal compiler error: in subreg_hard_regno, at emit-rtl.c:1088 Please submit a full bug report, with preprocessed source if appropriate. See <URL:http://gcc.gnu.org/bugs.html> for instructions.
Created attachment 4217 [details] preprocessed source
I can confirm the mainline ICE on 20030614, it only ICE on arm-linux not arm-elf. stage-4.c: In function `scheduler_4': stage-4.c:1310: internal compiler error: in subreg_hard_regno, at emit-rtl.c:1088 Please submit a full bug report. I think the 3.3 ICE would be the same as the mainline if checking is turned on.
Subject: Bug 11183 CVSROOT: /cvs/gcc Module name: gcc Changes by: rearnsha@gcc.gnu.org 2003-06-14 14:16:40 Modified files: gcc : ChangeLog gcc/config/arm : arm.c Log message: PR target/11183 * arm.c (output_move_double): Pass SImode to adjust_address. Patches: http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/ChangeLog.diff?cvsroot=gcc&r1=1.18210&r2=1.18211 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/arm/arm.c.diff?cvsroot=gcc&r1=1.280&r2=1.281
Subject: Bug 11183 CVSROOT: /cvs/gcc Module name: gcc Branch: gcc-3_3-branch Changes by: rearnsha@gcc.gnu.org 2003-06-14 14:20:54 Modified files: gcc : ChangeLog gcc/config/arm : arm.c Log message: PR target/11183 * arm.c (output_move_double): Pass SImode to adjust_address. Patches: http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/ChangeLog.diff?cvsroot=gcc&only_with_tag=gcc-3_3-branch&r1=1.16114.2.581&r2=1.16114.2.582 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/arm/arm.c.diff?cvsroot=gcc&only_with_tag=gcc-3_3-branch&r1=1.243.2.4&r2=1.243.2.5
Subject: Bug 11183 CVSROOT: /cvs/gcc Module name: gcc Changes by: rearnsha@gcc.gnu.org 2003-06-14 15:54:02 Modified files: gcc : ChangeLog gcc/config/arm : arm.h Log message: PR target/11183 * arm.h (CANNOT_CHANGE_MODE_CLASS): Define. Patches: http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/ChangeLog.diff?cvsroot=gcc&r1=1.18213&r2=1.18214 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/arm/arm.h.diff?cvsroot=gcc&r1=1.194&r2=1.195
Ohh! Two bugs in one report... The change_address bug was due to the fact that 1020 is a legal offset to an LDF instruction, but 1024 is not. Thus when we break the address into parts so that we can use LDR instructions we get an invalid offset. Fortunately, 1024 is a leagal offset for an LDR instruction. Telling change_address to validate against SImode fixes this. The second bug is a checking failure. When trying to find a register that contained zero, reload had identified the fact that a floating point register had zero in a subword of a floating point value. However, it isn't possible to subreg an FPA register, and the compiler was generating a consistency abort in the checking code. This can be rectified by defining CANNOT_CHANGE_MODE_CLASS. Although this failure also appears on the branch if checking is enabled, fixing the abort does not cause different code to be output. It seams sensible therefore not to apply the second patch to the branch.
*** Bug 10206 has been marked as a duplicate of this bug. ***