The last couple of years have seen GCC taking momentum in the embedded system industry, and also as a platform for advanced research in program analysis, transformation and optimization. The HiPEAC European Research Network and SARC European Integrated Project have decided to support GCC as a compiler platform for research and development in compilation for high-performance and embedded systems. It encourages researchers from inside and outside the network to share experience, projects, and prototypes based on this common platform.

Optimization Course

A course on GCC for Optimization Research was presented by Albert Cohen at the ACACES 2006 International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems, sponsored by HiPEAC.

Contents

It covers recent, ongoing and planned research projects involving GCC as a compiler platform. Starting from a brief presentation of GCC and its ecosystem, it explores both evolutionary and revolutionary program analyses, representations and transformations, emphasizing their design and implementation in development branches of GCC. In particular, it describes a research project in automatic loop transformation and parallelization, based on the recent inclusion of OpenMP parallel programming extensions; this will give an opportunity to survey key features of the interprocedural and middle-end frameworks introduced with GCC's 4.0 release. It also describes lower level research in retargettable vectorization, optimization and code generation for embedded VLIW processors; this leads to the exploration of the power and legacy of GCC's retargettable back-end, a key element of its success as a production compiler.

Support material

Optimization Tutorial

A Tutorial on Middle-End and Back-End Optimization in GCC was organized in May 2006 by HiPEAC and SARC, by Albert Cohen (INRIA), Zbignew Chamski (Philips), Ayal Zaks (IBM), Georges Silber (École des Mines de Paris), and Sebastian Pop (École des Mines de Paris).

Contents

This tutorial is an attempt to bootstrap new research and developments involving GCC, and to help those already involved in GCC-related projects to get support and answers. The targeted audience is the compilation/architecture researcher/engineer from industry or academia with a good background in textbook compilation and optimization. Prior knowledge of a compiler infrastructure is not assumed. Conversely, people with a lot of experience should be able to retrieve useful information and practice from this tutorial.

The main part of the tutorial describes the organization and behavior of the main compilation phases. To make the presentation very concrete and immediately useful to the attendees, it is followed by two practical examples of the design, the implementation and the test of a new phase:

  1. high-level program transformation for the typed SSA-form representation, through the design of a new optimization based on loop distribution, an optimization that is not currently offered by GCC;
  2. low-level code generation and back-end retargetting, through a automatic vectorization example for SIMD instructions not currently supported by GCC (clipping).

Support material

Before version 4, code optimizations in GCC were done in the back-end, at the RTL level. Starting with version 4, GCC adopted a new infrastructure, where all front-ends generate an intermediate representation named GIMPLE. This intermediate representation is mainly a typed three address code where high level constructs such as loops, conditions, function calls can still be used. A normalized SSA representation is derived from this intermediate representation, facilitating the design and implementation of scalable, aggressive analyzes and optimizations. To illustrate the use of this representation, we detail the implementation of a simple but realistic optimization pass (triggered by a specific optimization flag): loop distribution (and Allen, Callahan and Kennedy's algorithm).

The low-level RTL representation is now dedicated to target-specific analyses, transformations and code generation purposes. Considering both the GIMPLE and RTL representations, we show how to quickly provide GCC with a generic and retargetable support for (SIMD) saturated arithmetic. We walk into the instruction and machine description formats and mechanisms, and investigate important caveats associated with the interplay of instruction selection, scheduling and register allocation. Practical examples will focus on the PowerPC and x86 instruction sets.

Here is a patch against GCC 4.1 (svn://gcc.gnu.org/svn/gcc/tags/gcc_4_1_0_release). The patch should apply smoothly to further 4.1.x and 4.2.x releases as well.

Here is a patch against GCC 4.1 (svn://gcc.gnu.org/svn/gcc/tags/gcc_4_1_0_release). The patch should apply smoothly to further 4.1.x and 4.2.x releases as well.

None: OptimizationCourse (last edited 2008-01-10 19:38:40 by localhost)