2006-08-21 Paolo Bonzini * addresses.h (base_reg_class): Stop using MODE_BASE_REG_REG_CLASS. (ok_for_base_p_1): Likewise, stop using REGNO_MODE_OK_FOR_REG_BASE_P. * config/arm/arm.h (BASE_REG_CLASS): Remove. (MODE_BASE_REG_CLASS): Redefine as... (MODE_CODE_BASE_REG_CLASS): ... this. Test for reg+reg, use GET_MODE_SIZE instead of testing for SImode. (MODE_BASE_REG_REG_CLASS): Remove. (ARM_REGNO_OK_FOR_INDEX_P, THUMB_REGNO_OK_FOR_INDEX_P): New. (THUMB_REGNO_MODE_OK_FOR_BASE_P): Redefine as... (THUMB_REGNO_MODE_CODE_OK_FOR_BASE_P): ... this. Test for reg+reg. (REGNO_MODE_OK_FOR_BASE_P): Redefine as... (REGNO_MODE_CODE_OK_FOR_BASE_P): ... this. Use new Thumb macro. (REGNO_OK_FOR_INDEX_P): Use new macros above. * doc/tm.texi (MODE_BASE_REG_REG_CLASS, REGNO_MODE_OK_FOR_REG_BASE_P): Remove documentation. Index: addresses.h =================================================================== *** addresses.h (revision 116288) --- addresses.h (working copy) *************** base_reg_class (enum machine_mode mode A *** 30,39 **** #ifdef MODE_CODE_BASE_REG_CLASS return MODE_CODE_BASE_REG_CLASS (mode, outer_code, index_code); #else - #ifdef MODE_BASE_REG_REG_CLASS - if (index_code == REG) - return MODE_BASE_REG_REG_CLASS (mode); - #endif #ifdef MODE_BASE_REG_CLASS return MODE_BASE_REG_CLASS (mode); #else --- 30,35 ---- *************** ok_for_base_p_1 (unsigned regno, enum ma *** 55,64 **** #ifdef REGNO_MODE_CODE_OK_FOR_BASE_P return REGNO_MODE_CODE_OK_FOR_BASE_P (regno, mode, outer_code, index_code); #else - #ifdef REGNO_MODE_OK_FOR_REG_BASE_P - if (index_code == REG) - return REGNO_MODE_OK_FOR_REG_BASE_P (regno, mode); - #endif #ifdef REGNO_MODE_OK_FOR_BASE_P return REGNO_MODE_OK_FOR_BASE_P (regno, mode); #else --- 51,56 ---- Index: config/arm/arm.h =================================================================== *** config/arm/arm.h (revision 116289) --- config/arm/arm.h (working copy) *************** enum reg_class *** 1042,1059 **** /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) - #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) /* For the Thumb the high registers cannot be used as base registers when addressing quantities in QI or HI mode; if we don't know the ! mode, then we must be conservative. */ ! #define MODE_BASE_REG_CLASS(MODE) \ (TARGET_ARM ? GENERAL_REGS : \ ! (((MODE) == SImode) ? BASE_REGS : LO_REGS)) ! ! /* For Thumb we can not support SP+reg addressing, so we return LO_REGS ! instead of BASE_REGS. */ ! #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows registers explicitly used in the rtl to be used as spill registers --- 1042,1056 ---- /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) /* For the Thumb the high registers cannot be used as base registers when addressing quantities in QI or HI mode; if we don't know the ! mode, then we must be conservative. In addition, for Thumb we ! we can not support SP+reg addressing, so we return LO_REGS ! instead of BASE_REGS for reg+reg addresses. */ ! #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \ (TARGET_ARM ? GENERAL_REGS : \ ! (INDEX) != REG && GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS : LO_REGS) /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows registers explicitly used in the rtl to be used as spill registers *************** enum reg_class *** 1172,1178 **** GEN_INT (high)), \ GEN_INT (low)); \ push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ ! MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \ VOIDmode, 0, 0, OPNUM, TYPE); \ goto WIN; \ } \ --- 1169,1175 ---- GEN_INT (high)), \ GEN_INT (low)); \ push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ ! MODE_CODE_BASE_REG_CLASS (MODE, MEM, SCRATCH), GET_MODE (X), \ VOIDmode, 0, 0, OPNUM, TYPE); \ goto WIN; \ } \ *************** typedef struct *** 1727,1751 **** || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) ! #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ ! (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ ! || (GET_MODE_SIZE (MODE) >= 4 \ && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) ! #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ ! (TARGET_THUMB \ ! ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ : ARM_REGNO_OK_FOR_BASE_P (REGNO)) ! /* Nonzero if X can be the base register in a reg+reg addressing mode. ! For Thumb, we can not use SP + reg, so reject SP. */ ! #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ ! REGNO_OK_FOR_INDEX_P (X) ! ! /* For ARM code, we don't care about the mode, but for Thumb, the index ! must be suitable for use in a QImode load. */ ! #define REGNO_OK_FOR_INDEX_P(REGNO) \ ! REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) /* Maximum number of registers that can appear in a valid memory address. Shifts in addresses can't be by a register. */ --- 1724,1751 ---- || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) ! /* On the ARM, don't allow the pc to be used. */ ! #define ARM_REGNO_OK_FOR_INDEX_P(REGNO) \ ! ARM_REGNO_OK_FOR_BASE_P(REGNO) ! ! #define THUMB_REGNO_MODE_CODE_OK_FOR_BASE_P(REGNO, MODE, OUTER, INDEX) \ ! (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ ! || ((INDEX) != REG && GET_MODE_SIZE (MODE) >= 4 \ && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) ! /* On the thumb, never allow SP to be used as index. */ ! #define THUMB_REGNO_OK_FOR_INDEX_P(REGNO) \ ! TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) ! ! #define REGNO_MODE_CODE_OK_FOR_BASE_P(REGNO, MODE, OUTER, INDEX) \ ! (TARGET_THUMB \ ! ? THUMB_REGNO_MODE_CODE_OK_FOR_BASE_P (REGNO, MODE, OUTER, INDEX) \ : ARM_REGNO_OK_FOR_BASE_P (REGNO)) ! #define REGNO_OK_FOR_INDEX_P(REGNO) \ ! (TARGET_THUMB \ ! ? THUMB_REGNO_OK_FOR_INDEX_P (REGNO) \ ! : ARM_REGNO_OK_FOR_INDEX_P (REGNO)) /* Maximum number of registers that can appear in a valid memory address. Shifts in addresses can't be by a register. */ Index: doc/tm.texi =================================================================== *** doc/tm.texi (revision 116286) --- doc/tm.texi (working copy) *************** the selection of a base register in a mo *** 2295,2307 **** @code{BASE_REG_CLASS}. @end defmac - @defmac MODE_BASE_REG_REG_CLASS (@var{mode}) - A C expression whose value is the register class to which a valid - base register must belong in order to be used in a base plus index - register address. You should define this macro if base plus index - addresses have different requirements than other base register uses. - @end defmac - @defmac MODE_CODE_BASE_REG_CLASS (@var{mode}, @var{outer_code}, @var{index_code}) A C expression whose value is the register class to which a valid base register must belong. @var{outer_code} and @var{index_code} define the --- 2295,2300 ---- *************** that appear outside a @code{MEM}, i.e. a *** 2337,2354 **** @end defmac - @defmac REGNO_MODE_OK_FOR_REG_BASE_P (@var{num}, @var{mode}) - A C expression which is nonzero if register number @var{num} is suitable for - use as a base register in base plus index operand addresses, accessing - memory in mode @var{mode}. It may be either a suitable hard register or a - pseudo register that has been allocated such a hard register. You should - define this macro if base plus index addresses have different requirements - than other base register uses. - - Use of this macro is deprecated; please use the more general - @code{REGNO_MODE_CODE_OK_FOR_BASE_P}. - @end defmac - @defmac REGNO_MODE_CODE_OK_FOR_BASE_P (@var{num}, @var{mode}, @var{outer_code}, @var{index_code}) A C expression that is just like @code{REGNO_MODE_OK_FOR_BASE_P}, except that that expression may examine the context in which the register appears in the --- 2330,2335 ----