These ‘-m’ options are supported on the SPARC:
To be fully SVR4 ABI-compliant at the cost of some performance loss,
specify -mno-app-regs. You should compile libraries and system
software with this option.
With -mno-flat (the default), the compiler generates save/restore
instructions (except for leaf functions). This is the normal operating mode.
-msoft-float changes the calling convention in the output file;
therefore, it is only useful if you compile all of a program with
this option. In particular, you need to compile libgcc.a, the
library that comes with GCC, with -msoft-float in order for
this to work.
As of this writing, there are no SPARC implementations that have hardware
support for the quad-word floating-point instructions. They all invoke
a trap handler for one of these instructions, and then the trap handler
emulates the effect of the instruction. Because of the trap handler overhead,
this is much slower than calling the ABI library routines. Thus the
-msoft-quad-float option is the default.
With -munaligned-doubles, GCC assumes that doubles have 8-byte
alignment only if they are contained in another type, or if they have an
absolute address. Otherwise, it assumes they have 4-byte alignment.
Specifying this option avoids some rare compatibility problems with code
generated by other compilers. It is not the default because it results
in a performance loss, especially for floating-point code.
stdinstructions for copies in structure assignment, in place of twice as many
stpairs. However, the use of this changed alignment directly violates the SPARC ABI. Thus, it's intended only for use on targets where the developer acknowledges that their resulting code is not directly in line with the rules of the ABI.
Native Solaris and GNU/Linux toolchains also support the value ‘native’, which selects the best architecture option for the host processor. -mcpu=native has no effect if GCC does not recognize the processor.
Default instruction scheduling parameters are used for values that select an architecture and not an implementation. These are ‘v7’, ‘v8’, ‘sparclite’, ‘sparclet’, ‘v9’.
Here is a list of each supported architecture and their supported implementations.
By default (unless configured otherwise), GCC generates code for the V7 variant of the SPARC architecture. With -mcpu=cypress, the compiler additionally optimizes it for the Cypress CY7C602 chip, as used in the SPARCStation/SPARCServer 3xx series. This is also appropriate for the older SPARCStation 1, 2, IPX etc.
With -mcpu=v8, GCC generates code for the V8 variant of the SPARC architecture. The only difference from V7 code is that the compiler emits the integer multiply and integer divide instructions which exist in SPARC-V8 but not in SPARC-V7. With -mcpu=supersparc, the compiler additionally optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and 2000 series.
With -mcpu=sparclite, GCC generates code for the SPARClite variant of
the SPARC architecture. This adds the integer multiply, integer divide step
and scan (
ffs) instructions which exist in SPARClite but not in SPARC-V7.
With -mcpu=f930, the compiler additionally optimizes it for the
Fujitsu MB86930 chip, which is the original SPARClite, with no FPU. With
-mcpu=f934, the compiler additionally optimizes it for the Fujitsu
MB86934 chip, which is the more recent SPARClite with FPU.
With -mcpu=sparclet, GCC generates code for the SPARClet variant of
the SPARC architecture. This adds the integer multiply, multiply/accumulate,
integer divide step and scan (
ffs) instructions which exist in SPARClet
but not in SPARC-V7. With -mcpu=tsc701, the compiler additionally
optimizes it for the TEMIC SPARClet chip.
With -mcpu=v9, GCC generates code for the V9 variant of the SPARC
architecture. This adds 64-bit integer and floating-point move instructions,
3 additional floating-point condition code registers and conditional move
instructions. With -mcpu=ultrasparc, the compiler additionally
optimizes it for the Sun UltraSPARC I/II/IIi chips. With
-mcpu=ultrasparc3, the compiler additionally optimizes it for the
Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With
-mcpu=niagara, the compiler additionally optimizes it for
Sun UltraSPARC T1 chips. With -mcpu=niagara2, the compiler
additionally optimizes it for Sun UltraSPARC T2 chips. With
-mcpu=niagara3, the compiler additionally optimizes it for Sun
UltraSPARC T3 chips. With -mcpu=niagara4, the compiler
additionally optimizes it for Sun UltraSPARC T4 chips.
The same values for -mcpu=cpu_type can be used for
-mtune=cpu_type, but the only useful values are those
that select a particular CPU implementation. Those are ‘cypress’,
‘supersparc’, ‘hypersparc’, ‘leon’, ‘leon3’, ‘f930’,
‘f934’, ‘sparclite86x’, ‘tsc701’, ‘ultrasparc’,
‘ultrasparc3’, ‘niagara’, ‘niagara2’, ‘niagara3’ and
‘niagara4’. With native Solaris and GNU/Linux toolchains, ‘native’
can also be used.
These ‘-m’ options are supported in addition to the above on SPARC-V9 processors in 64-bit environments:
These memory models are formally defined in Appendix D of the Sparc V9
architecture manual, as set in the processor's