In processor names, a final `000' can be abbreviated as `k' (for example, `-march=r2k'). Prefixes are optional, and `vr' may be written `r'.
GCC defines two macros based on the value of this option. The first is `_MIPS_ARCH', which gives the name of target architecture, as a string. The second has the form `_MIPS_ARCH_foo', where foo is the capitalized value of `_MIPS_ARCH'. For example, `-march=r2000' will set `_MIPS_ARCH' to `"r2000"' and define the macro `_MIPS_ARCH_R2000'.
Note that the `_MIPS_ARCH' macro uses the processor names given
above. In other words, it will have the full prefix and will not
abbreviate `000' as `k'. In the case of `from-abi',
the macro names the resolved architecture (either `"mips1"' or
`"mips3"'). It names the default architecture when no
-march option is given.
When this option is not used, GCC will optimize for the processor specified by -march. By using -march and -mtune together, it is possible to generate code that will run on a family of processors, but optimize the code for one particular member of that family.
`-mtune' defines the macros `_MIPS_TUNE' and
`_MIPS_TUNE_foo', which work in the same way as the
`-march' ones described above.
Note that the EABI has a 32-bit and a 64-bit variant. GCC normally generates 64-bit code when you select a 64-bit architecture, but you can use -mgp32 to get 32-bit code instead.
For information about the O64 ABI, see
GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it will only work if the GOT is smaller than about 64k. Anything larger will cause the linker to report an error such as:
relocation truncated to fit: R_MIPS_GOT16 foobar
If this happens, you should recompile your code with -mxgot. It should then work with very large GOTs, although it will also be less efficient, since it will take three instructions to fetch the value of a global symbol.
Note that some linkers can create multiple GOTs. If you have such a linker, you should only need to use -mxgot when a single object file accesses more than 64k's worth of GOT entries. Very few do.
These options have no effect unless GCC is generating position
longtypes to be 64 bits wide. See -mlong32 for an explanation of the default and the way that the pointer size is determined.
int, and pointer types to be 32 bits wide.
The default size of
longs and pointers depends on
the ABI. All the supported ABIs use 32-bit
ints. The n64 ABI
longs, as does the 64-bit EABI; the others use
longs. Pointers are the same size as
or the same size as integer registers, whichever is smaller.
All modules should be compiled with the same -G num
constvariables in the read-only data section. This option is only meaningful in conjunction with -membedded-data.
%lo()assembler relocation operators. This option has been superseded by -mexplicit-relocs but is retained for backwards compatibility.
-mexplicit-relocs is the default if GCC was configured
to use an assembler that supports relocation operators.
SIGFPE). Use -mdivide-traps to allow conditional traps on architectures that support them and -mdivide-breaks to force the use of breaks.
The default is usually -mdivide-traps, but this can be
overridden at configure time using --with-divide=breaks.
Divide-by-zero checks can be completely disabled using
memcpy()for non-trivial block moves. The default is -mno-memcpy, which allows GCC to inline most constant-sized copies.
jalinstruction. Calling functions using
jalis more efficient but requires the caller and callee to be in the same 256 megabyte segment.
This option has no effect on abicalls code. The default is
mulinstructions, as provided by the R4650 ISA.
When multiply-accumulate instructions are used, the intermediate
product is calculated to infinite precision and is not subject to
the FCSR Flush to Zero bit. This may be undesirable in some
dmultudoes not always produce the correct result.
ddivdo not always produce the correct result if one of the operands is negative.
Other VR4120 errata require a nop to be inserted between certain pairs of
instructions. These errata are handled by the assembler, not by GCC itself.
mfhierrata. The workarounds are implemented by the assembler rather than by GCC, although GCC will avoid using
mfhiif the VR4130
dmacchiinstructions are available instead.
_flush_func(), that is, the address of the memory range for which the cache is being flushed, the size of the memory range, and the number 3 (to flush both caches). The default depends on the target GCC was configured for, but commonly is either `_flush_func' or `__cpu_flush'.
For instance, on the SB-1, if FP exceptions are disabled, and we are emitting
64-bit code, then we can use both FP pipes. Otherwise, we can only use one
This option only has an effect when optimizing for the VR4130. It normally makes code faster, but at the expense of making it bigger. It is enabled by default at optimization level -O3.