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3.17.18 MIPS Options

Generate big-endian code.
Generate little-endian code. This is the default for `mips*el-*-*' configurations.
Generate code that will run on arch, which can be the name of a generic MIPS ISA, or the name of a particular processor. The ISA names are: `mips1', `mips2', `mips3', `mips4', `mips32', `mips32r2', and `mips64'. The processor names are: `4kc', `4kp', `5kc', `20kc', `m4k', `r2000', `r3000', `r3900', `r4000', `r4400', `r4600', `r4650', `r6000', `r8000', `rm7000', `rm9000', `orion', `sb1', `vr4100', `vr4111', `vr4120', `vr4130', `vr4300', `vr5000', `vr5400' and `vr5500'. The special value `from-abi' selects the most compatible architecture for the selected ABI (that is, `mips1' for 32-bit ABIs and `mips3' for 64-bit ABIs).

In processor names, a final `000' can be abbreviated as `k' (for example, `-march=r2k'). Prefixes are optional, and `vr' may be written `r'.

GCC defines two macros based on the value of this option. The first is `_MIPS_ARCH', which gives the name of target architecture, as a string. The second has the form `_MIPS_ARCH_foo', where foo is the capitalized value of `_MIPS_ARCH'. For example, `-march=r2000' will set `_MIPS_ARCH' to `"r2000"' and define the macro `_MIPS_ARCH_R2000'.

Note that the `_MIPS_ARCH' macro uses the processor names given above. In other words, it will have the full prefix and will not abbreviate `000' as `k'. In the case of `from-abi', the macro names the resolved architecture (either `"mips1"' or `"mips3"'). It names the default architecture when no -march option is given.

Optimize for arch. Among other things, this option controls the way instructions are scheduled, and the perceived cost of arithmetic operations. The list of arch values is the same as for -march.

When this option is not used, GCC will optimize for the processor specified by -march. By using -march and -mtune together, it is possible to generate code that will run on a family of processors, but optimize the code for one particular member of that family.

`-mtune' defines the macros `_MIPS_TUNE' and `_MIPS_TUNE_foo', which work in the same way as the `-march' ones described above.

Equivalent to `-march=mips1'.
Equivalent to `-march=mips2'.
Equivalent to `-march=mips3'.
Equivalent to `-march=mips4'.
Equivalent to `-march=mips32'.
Equivalent to `-march=mips32r2'.
Equivalent to `-march=mips64'.
Use (do not use) the MIPS16 ISA.
Generate code for the given ABI.

Note that the EABI has a 32-bit and a 64-bit variant. GCC normally generates 64-bit code when you select a 64-bit architecture, but you can use -mgp32 to get 32-bit code instead.

For information about the O64 ABI, see

Generate (do not generate) SVR4-style position-independent code. -mabicalls is the default for SVR4-based systems.
Lift (do not lift) the usual restrictions on the size of the global offset table.

GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it will only work if the GOT is smaller than about 64k. Anything larger will cause the linker to report an error such as:

          relocation truncated to fit: R_MIPS_GOT16 foobar

If this happens, you should recompile your code with -mxgot. It should then work with very large GOTs, although it will also be less efficient, since it will take three instructions to fetch the value of a global symbol.

Note that some linkers can create multiple GOTs. If you have such a linker, you should only need to use -mxgot when a single object file accesses more than 64k's worth of GOT entries. Very few do.

These options have no effect unless GCC is generating position independent code.

Assume that general-purpose registers are 32 bits wide.
Assume that general-purpose registers are 64 bits wide.
Assume that floating-point registers are 32 bits wide.
Assume that floating-point registers are 64 bits wide.
Use floating-point coprocessor instructions.
Do not use floating-point coprocessor instructions. Implement floating-point calculations using library calls instead.
Assume that the floating-point coprocessor only supports single-precision operations.
Assume that the floating-point coprocessor supports double-precision operations. This is the default.
Use (do not use) paired-single floating-point instructions. See MIPS Paired-Single Support. This option can only be used when generating 64-bit code and requires hardware floating-point support to be enabled.
Use (do not use) the MIPS-3D ASE. See MIPS-3D Built-in Functions. The option -mips3d implies -mpaired-single.
Force int and long types to be 64 bits wide. See -mlong32 for an explanation of the default and the way that the pointer size is determined.

This option has been deprecated and will be removed in a future release.

Force long types to be 64 bits wide. See -mlong32 for an explanation of the default and the way that the pointer size is determined.
Force long, int, and pointer types to be 32 bits wide.

The default size of ints, longs and pointers depends on the ABI. All the supported ABIs use 32-bit ints. The n64 ABI uses 64-bit longs, as does the 64-bit EABI; the others use 32-bit longs. Pointers are the same size as longs, or the same size as integer registers, whichever is smaller.

Assume (do not assume) that all symbols have 32-bit values, regardless of the selected ABI. This option is useful in combination with -mabi=64 and -mno-abicalls because it allows GCC to generate shorter and faster references to symbolic addresses.
-G num
Put global and static items less than or equal to num bytes into the small data or bss section instead of the normal data or bss section. This allows the data to be accessed using a single instruction.

All modules should be compiled with the same -G num value.

Allocate variables to the read-only data section first if possible, then next in the small data section if possible, otherwise in data. This gives slightly slower code than the default, but reduces the amount of RAM required when executing, and thus may be preferred for some embedded systems.
Put uninitialized const variables in the read-only data section. This option is only meaningful in conjunction with -membedded-data.
Enable (disable) use of the %hi() and %lo() assembler relocation operators. This option has been superseded by -mexplicit-relocs but is retained for backwards compatibility.
Use (do not use) assembler relocation operators when dealing with symbolic addresses. The alternative, selected by -mno-explicit-relocs, is to use assembler macros instead.

-mexplicit-relocs is the default if GCC was configured to use an assembler that supports relocation operators.

Trap (do not trap) on integer division by zero. The default is -mcheck-zero-division.
MIPS systems check for division by zero by generating either a conditional trap or a break instruction. Using traps results in smaller code, but is only supported on MIPS II and later. Also, some versions of the Linux kernel have a bug that prevents trap from generating the proper signal (SIGFPE). Use -mdivide-traps to allow conditional traps on architectures that support them and -mdivide-breaks to force the use of breaks.

The default is usually -mdivide-traps, but this can be overridden at configure time using --with-divide=breaks. Divide-by-zero checks can be completely disabled using -mno-check-zero-division.

Force (do not force) the use of memcpy() for non-trivial block moves. The default is -mno-memcpy, which allows GCC to inline most constant-sized copies.
Disable (do not disable) use of the jal instruction. Calling functions using jal is more efficient but requires the caller and callee to be in the same 256 megabyte segment.

This option has no effect on abicalls code. The default is -mno-long-calls.

Enable (disable) use of the mad, madu and mul instructions, as provided by the R4650 ISA.
Enable (disable) use of the floating point multiply-accumulate instructions, when they are available. The default is -mfused-madd.

When multiply-accumulate instructions are used, the intermediate product is calculated to infinite precision and is not subject to the FCSR Flush to Zero bit. This may be undesirable in some circumstances.

Tell the MIPS assembler to not run its preprocessor over user assembler files (with a `.s' suffix) when assembling them.
Work around certain R4000 CPU errata:
Work around certain R4400 CPU errata:
Work around certain VR4120 errata: The workarounds for the division errata rely on special functions in libgcc.a. At present, these functions are only provided by the mips64vr*-elf configurations.

Other VR4120 errata require a nop to be inserted between certain pairs of instructions. These errata are handled by the assembler, not by GCC itself.

Work around the VR4130 mflo/mfhi errata. The workarounds are implemented by the assembler rather than by GCC, although GCC will avoid using mflo and mfhi if the VR4130 macc, macchi, dmacc and dmacchi instructions are available instead.
Work around certain SB-1 CPU core errata. (This flag currently works around the SB-1 revision 2 “F1” and “F2” floating point errata.)
Specifies the function to call to flush the I and D caches, or to not call any such function. If called, the function must take the same arguments as the common _flush_func(), that is, the address of the memory range for which the cache is being flushed, the size of the memory range, and the number 3 (to flush both caches). The default depends on the target GCC was configured for, but commonly is either `_flush_func' or `__cpu_flush'.
Enable or disable use of Branch Likely instructions, regardless of the default for the selected architecture. By default, Branch Likely instructions may be generated if they are supported by the selected architecture. An exception is for the MIPS32 and MIPS64 architectures and processors which implement those architectures; for those, Branch Likely instructions will not be generated by default because the MIPS32 and MIPS64 architectures specifically deprecate their use.
Specifies whether FP exceptions are enabled. This affects how we schedule FP instructions for some processors. The default is that FP exceptions are enabled.

For instance, on the SB-1, if FP exceptions are disabled, and we are emitting 64-bit code, then we can use both FP pipes. Otherwise, we can only use one FP pipe.

The VR4130 pipeline is two-way superscalar, but can only issue two instructions together if the first one is 8-byte aligned. When this option is enabled, GCC will align pairs of instructions that it thinks should execute in parallel.

This option only has an effect when optimizing for the VR4130. It normally makes code faster, but at the expense of making it bigger. It is enabled by default at optimization level -O3.