-m options are defined for Motorola 88k architectures:
identdirective in the assembler output recording the source file name, compiler name and version, timestamp, and compilation flags used.
-mocs-frame-position; other 88k configurations have the default
r0, which allows loading a value using a single instruction (rather than the usual two). You control which data references are affected by specifying num with this option. For example, if you specify
-mshort-data-512, then the data references affected are those involving displacements of less than 512 bytes.
is not effective for num greater than 64k.
The order of memory references made by the MC88110 processor does not always match the order of the instructions requesting those references. In particular, a load instruction may execute before a preceding store instruction. Such reordering violates sequential consistency of volatile memory references, when there are multiple processors. When consistency must be guaranteed, GCC generates special instructions, as needed, to force execution in the proper order.
The MC88100 processor does not reorder memory references and so
always provides sequential consistency. However, by default, GCC
generates the special instructions to guarantee consistency
even when you use
-m88100, so that the code may be run on an
MC88110 processor. If you intend to run your code only on the
MC88100 processor, you may use
The extra code generated to guarantee consistency may affect the
performance of your application. If you know that you can safely
forgo this guarantee, you may use
-msvr4) or off (
-msvr3) compiler extensions related to System V release 4 (SVr4). This controls the following:
-msvr4makes the C preprocessor recognize
#pragma weakthat is used on System V release 4.
-msvr4makes GCC issue additional declaration directives used in SVr4.
-msvr4 is the default for the m88k-motorola-sysv4 and
m88k-dg-dgux m88k configurations.
-msvr3 is the default for all
other m88k configurations.
Some models of the MC88100 processor fail to trap upon integer
division by zero under certain conditions. By default, when
compiling code that might be run on such a processor, GCC
generates code that explicitly checks for zero-valued divisors
and traps with exception number 503 when one is detected. Use of
-mno-check-zero-division suppresses such checking for code
generated to run on an MC88100 processor.
GCC assumes that the MC88110 processor correctly detects all instances
of integer division by zero. When
-m88110 is specified, no
explicit checks for zero-valued divisors are generated, and both
On the MC88100 processor the signed integer division instruction div) traps to the operating system on a negative operand. The operating system transparently completes the operation, but at a large cost in execution time. By default, when compiling code that might be run on an MC88100 processor, GCC emulates signed integer division using the unsigned integer division instruction divu), thereby avoiding the large penalty of a trap to the operating system. Such emulation has its own, smaller, execution cost in both time and space. To the extent that your code's important signed integer division operations are performed on two nonnegative operands, it may be desirable to use the div instruction directly.
On the MC88110 processor the div instruction (also known as the
divs instruction) processes negative operands without trapping to
the operating system. When
-m88110 is specified,
-muse-div-instruction is ignored, and the div instruction is used
for signed integer division.
Note that the result of dividing
INT_MIN by -1 is undefined. In
particular, the behavior of such a division with and without
-muse-div-instruction may differ.