[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20. Machine Descriptions

A machine description has two parts: a file of instruction patterns (`.md' file) and a C header file of macro definitions.

The `.md' file for a target machine contains a pattern for each instruction that the target machine supports (or at least each instruction that is worth telling the compiler about). It may also contain comments. A semicolon causes the rest of the line to be a comment, unless the semicolon is inside a quoted string.

See the next chapter for information on the C header file.

20.1 Overview of How the Machine Description is Used  How the machine description is used.
20.2 Everything about Instruction Patterns  How to write instruction patterns.
20.3 Example of define_insn  An explained example of a define_insn pattern.
20.4 RTL Template  The RTL template defines what insns match a pattern.
20.5 Output Templates and Operand Substitution  The output template says how to make assembler code from such an insn.
20.6 C Statements for Assembler Output  For more generality, write C code to output the assembler code.
20.7 Operand Constraints  When not all operands are general operands.
20.8 Standard Pattern Names For Generation  Names mark patterns to use for code generation.
20.9 When the Order of Patterns Matters  When the order of patterns makes a difference.
20.10 Interdependence of Patterns  Having one pattern may make you need another.
20.11 Defining Jump Instruction Patterns  Special considerations for patterns for jump insns.
20.12 Defining Looping Instruction Patterns  How to define patterns for special looping insns.
20.13 Canonicalization of Instructions  
20.14 Defining RTL Sequences for Code Generation  Generating a sequence of several RTL insns for a standard operation.
20.15 Defining How to Split Instructions  Splitting Instructions into Multiple Instructions.
20.16 Machine-Specific Peephole Optimizers  Defining machine-specific peephole optimizations.
20.17 Instruction Attributes  Specifying the value of attributes for generated insns.
20.18 Conditional Execution  Generating define_insn patterns for predication.
20.19 Constant Definitions  Defining symbolic constants that can be used in the md file.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.1 Overview of How the Machine Description is Used

There are three main conversions that happen in the compiler:

  1. The front end reads the source code and builds a parse tree.

  2. The parse tree is used to generate an RTL insn list based on named instruction patterns.

  3. The insn list is matched against the RTL templates to produce assembler code.

For the generate pass, only the names of the insns matter, from either a named define_insn or a define_expand. The compiler will choose the pattern with the right name and apply the operands according to the documentation later in this chapter, without regard for the RTL template or operand constraints. Note that the names the compiler looks for are hard-coded in the compiler--it will ignore unnamed patterns and patterns with names it doesn't know about, but if you don't provide a named pattern it needs, it will abort.

If a define_insn is used, the template given is inserted into the insn list. If a define_expand is used, one of three things happens, based on the condition logic. The condition logic may manually create new insns for the insn list, say via emit_insn(), and invoke DONE. For certain named patterns, it may invoke FAIL to tell the compiler to use an alternate way of performing that task. If it invokes neither DONE nor FAIL, the template given in the pattern is inserted, as if the define_expand were a define_insn.

Once the insn list is generated, various optimization passes convert, replace, and rearrange the insns in the insn list. This is where the define_split and define_peephole patterns get used, for example.

Finally, the insn list's RTL is matched up with the RTL templates in the define_insn patterns, and those patterns are used to emit the final assembly code. For this purpose, each named define_insn acts like it's unnamed, since the names are ignored.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.2 Everything about Instruction Patterns

Each instruction pattern contains an incomplete RTL expression, with pieces to be filled in later, operand constraints that restrict how the pieces can be filled in, and an output pattern or C code to generate the assembler output, all wrapped up in a define_insn expression.

A define_insn is an RTL expression containing four or five operands:

  1. An optional name. The presence of a name indicate that this instruction pattern can perform a certain standard job for the RTL-generation pass of the compiler. This pass knows certain names and will use the instruction patterns with those names, if the names are defined in the machine description.

    The absence of a name is indicated by writing an empty string where the name should go. Nameless instruction patterns are never used for generating RTL code, but they may permit several simpler insns to be combined later on.

    Names that are not thus known and used in RTL-generation have no effect; they are equivalent to no name at all.

    For the purpose of debugging the compiler, you may also specify a name beginning with the `*' character. Such a name is used only for identifying the instruction in RTL dumps; it is entirely equivalent to having a nameless pattern for all other purposes.

  2. The RTL template (see section 20.4 RTL Template) is a vector of incomplete RTL expressions which show what the instruction should look like. It is incomplete because it may contain match_operand, match_operator, and match_dup expressions that stand for operands of the instruction.

    If the vector has only one element, that element is the template for the instruction pattern. If the vector has multiple elements, then the instruction pattern is a parallel expression containing the elements described.

  3. A condition. This is a string which contains a C expression that is the final test to decide whether an insn body matches this pattern.

    For a named pattern, the condition (if present) may not depend on the data in the insn being matched, but only the target-machine-type flags. The compiler needs to test these conditions during initialization in order to learn exactly which named instructions are available in a particular run.

    For nameless patterns, the condition is applied only when matching an individual insn, and only after the insn has matched the pattern's recognition template. The insn's operands may be found in the vector operands.

  4. The output template: a string that says how to output matching insns as assembler code. `%' in this string specifies where to substitute the value of an operand. See section 20.5 Output Templates and Operand Substitution.

    When simple substitution isn't general enough, you can specify a piece of C code to compute the output. See section 20.6 C Statements for Assembler Output.

  5. Optionally, a vector containing the values of attributes for insns matching this pattern. See section 20.17 Instruction Attributes.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.3 Example of define_insn

Here is an actual example of an instruction pattern, for the 68000/68020.

(define_insn "tstsi"
  [(set (cc0)
        (match_operand:SI 0 "general_operand" "rm"))]
{ if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
    return \"tstl %0\";
  return \"cmpl #0,%0\"; }")

This is an instruction that sets the condition codes based on the value of a general operand. It has no condition, so any insn whose RTL description has the form shown may be handled according to this pattern. The name `tstsi' means "test a SImode value" and tells the RTL generation pass that, when it is necessary to test such a value, an insn to do so can be constructed using this pattern.

The output control string is a piece of C code which chooses which output template to return based on the kind of operand and the specific type of CPU for which code is being generated.

`"rm"' is an operand constraint. Its meaning is explained below.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.4 RTL Template

The RTL template is used to define which insns match the particular pattern and how to find their operands. For named patterns, the RTL template also says how to construct an insn from specified operands.

Construction involves substituting specified operands into a copy of the template. Matching involves determining the values that serve as the operands in the insn being matched. Both of these activities are controlled by special expression types that direct matching and substitution of the operands.

(match_operand:m n predicate constraint)
This expression is a placeholder for operand number n of the insn. When constructing an insn, operand number n will be substituted at this point. When matching an insn, whatever appears at this position in the insn will be taken as operand number n; but it must satisfy predicate or this instruction pattern will not match at all.

Operand numbers must be chosen consecutively counting from zero in each instruction pattern. There may be only one match_operand expression in the pattern for each operand number. Usually operands are numbered in the order of appearance in match_operand expressions. In the case of a define_expand, any operand numbers used only in match_dup expressions have higher values than all other operand numbers.

predicate is a string that is the name of a C function that accepts two arguments, an expression and a machine mode. During matching, the function will be called with the putative operand as the expression and m as the mode argument (if m is not specified, VOIDmode will be used, which normally causes predicate to accept any mode). If it returns zero, this instruction pattern fails to match. predicate may be an empty string; then it means no test is to be done on the operand, so anything which occurs in this position is valid.

Most of the time, predicate will reject modes other than m---but not always. For example, the predicate address_operand uses m as the mode of memory ref that the address should be valid for. Many predicates accept const_int nodes even though their mode is VOIDmode.

constraint controls reloading and the choice of the best register class to use for a value, as explained later (see section 20.7 Operand Constraints).

People are often unclear on the difference between the constraint and the predicate. The predicate helps decide whether a given insn matches the pattern. The constraint plays no role in this decision; instead, it controls various decisions in the case of an insn which does match.

On CISC machines, the most common predicate is "general_operand". This function checks that the putative operand is either a constant, a register or a memory reference, and that it is valid for mode m.

For an operand that must be a register, predicate should be "register_operand". Using "general_operand" would be valid, since the reload pass would copy any non-register operands through registers, but this would make GCC do extra work, it would prevent invariant operands (such as constant) from being removed from loops, and it would prevent the register allocator from doing the best possible job. On RISC machines, it is usually most efficient to allow predicate to accept only objects that the constraints allow.

For an operand that must be a constant, you must be sure to either use "immediate_operand" for predicate, or make the instruction pattern's extra condition require a constant, or both. You cannot expect the constraints to do this work! If the constraints allow only constants, but the predicate allows something else, the compiler will crash when that case arises.

(match_scratch:m n constraint)
This expression is also a placeholder for operand number n and indicates that operand must be a scratch or reg expression.

When matching patterns, this is equivalent to

(match_operand:m n "scratch_operand" pred)

but, when generating RTL, it produces a (scratch:m) expression.

If the last few expressions in a parallel are clobber expressions whose operands are either a hard register or match_scratch, the combiner can add or delete them when necessary. See section 19.14 Side Effect Expressions.

(match_dup n)
This expression is also a placeholder for operand number n. It is used when the operand needs to appear more than once in the insn.

In construction, match_dup acts just like match_operand: the operand is substituted into the insn being constructed. But in matching, match_dup behaves differently. It assumes that operand number n has already been determined by a match_operand appearing earlier in the recognition template, and it matches only an identical-looking expression.

Note that match_dup should not be used to tell the compiler that a particular register is being used for two operands (example: add that adds one register to another; the second register is both an input operand and the output operand). Use a matching constraint (see section 20.7.1 Simple Constraints) for those. match_dup is for the cases where one operand is used in two places in the template, such as an instruction that computes both a quotient and a remainder, where the opcode takes two input operands but the RTL template has to refer to each of those twice; once for the quotient pattern and once for the remainder pattern.

(match_operator:m n predicate [operands...])
This pattern is a kind of placeholder for a variable RTL expression code.

When constructing an insn, it stands for an RTL expression whose expression code is taken from that of operand n, and whose operands are constructed from the patterns operands.

When matching an expression, it matches an expression if the function predicate returns nonzero on that expression and the patterns operands match the operands of the expression.

Suppose that the function commutative_operator is defined as follows, to match any expression whose operator is one of the commutative arithmetic operators of RTL and whose mode is mode:

commutative_operator (x, mode)
     rtx x;
     enum machine_mode mode;
  enum rtx_code code = GET_CODE (x);
  if (GET_MODE (x) != mode)
    return 0;
  return (GET_RTX_CLASS (code) == 'c'
          || code == EQ || code == NE);

Then the following pattern will match any RTL expression consisting of a commutative operator applied to two general operands:

(match_operator:SI 3 "commutative_operator"
  [(match_operand:SI 1 "general_operand" "g")
   (match_operand:SI 2 "general_operand" "g")])

Here the vector [operands...] contains two patterns because the expressions to be matched all contain two operands.

When this pattern does match, the two operands of the commutative operator are recorded as operands 1 and 2 of the insn. (This is done by the two instances of match_operand.) Operand 3 of the insn will be the entire commutative expression: use GET_CODE (operands[3]) to see which commutative operator was used.

The machine mode m of match_operator works like that of match_operand: it is passed as the second argument to the predicate function, and that function is solely responsible for deciding whether the expression to be matched "has" that mode.

When constructing an insn, argument 3 of the gen-function will specify the operation (i.e. the expression code) for the expression to be made. It should be an RTL expression, whose expression code is copied into a new expression whose operands are arguments 1 and 2 of the gen-function. The subexpressions of argument 3 are not used; only its expression code matters.

When match_operator is used in a pattern for matching an insn, it usually best if the operand number of the match_operator is higher than that of the actual operands of the insn. This improves register allocation because the register allocator often looks at operands 1 and 2 of insns to see if it can do register tying.

There is no way to specify constraints in match_operator. The operand of the insn which corresponds to the match_operator never has any constraints because it is never reloaded as a whole. However, if parts of its operands are matched by match_operand patterns, those parts may have constraints of their own.

(match_op_dup:m n[operands...])
Like match_dup, except that it applies to operators instead of operands. When constructing an insn, operand number n will be substituted at this point. But in matching, match_op_dup behaves differently. It assumes that operand number n has already been determined by a match_operator appearing earlier in the recognition template, and it matches only an identical-looking expression.

(match_parallel n predicate [subpat...])
This pattern is a placeholder for an insn that consists of a parallel expression with a variable number of elements. This expression should only appear at the top level of an insn pattern.

When constructing an insn, operand number n will be substituted at this point. When matching an insn, it matches if the body of the insn is a parallel expression with at least as many elements as the vector of subpat expressions in the match_parallel, if each subpat matches the corresponding element of the parallel, and the function predicate returns nonzero on the parallel that is the body of the insn. It is the responsibility of the predicate to validate elements of the parallel beyond those listed in the match_parallel.

A typical use of match_parallel is to match load and store multiple expressions, which can contain a variable number of elements in a parallel. For example,

(define_insn ""
  [(match_parallel 0 "load_multiple_operation"
     [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
           (match_operand:SI 2 "memory_operand" "m"))
      (use (reg:SI 179))
      (clobber (reg:SI 179))])]
  "loadm 0,0,%1,%2")

This example comes from `a29k.md'. The function load_multiple_operations is defined in `a29k.c' and checks that subsequent elements in the parallel are the same as the set in the pattern, except that they are referencing subsequent registers and memory locations.

An insn that matches this pattern might look like:

 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
  (use (reg:SI 179))
  (clobber (reg:SI 179))
  (set (reg:SI 21)
       (mem:SI (plus:SI (reg:SI 100)
                        (const_int 4))))
  (set (reg:SI 22)
       (mem:SI (plus:SI (reg:SI 100)
                        (const_int 8))))])

(match_par_dup n [subpat...])
Like match_op_dup, but for match_parallel instead of match_operator.

(match_insn predicate)
Match a complete insn. Unlike the other match_* recognizers, match_insn does not take an operand number.

The machine mode m of match_insn works like that of match_operand: it is passed as the second argument to the predicate function, and that function is solely responsible for deciding whether the expression to be matched "has" that mode.

(match_insn2 n predicate)
Match a complete insn.

The machine mode m of match_insn2 works like that of match_operand: it is passed as the second argument to the predicate function, and that function is solely responsible for deciding whether the expression to be matched "has" that mode.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.5 Output Templates and Operand Substitution

The output template is a string which specifies how to output the assembler code for an instruction pattern. Most of the template is a fixed string which is output literally. The character `%' is used to specify where to substitute an operand; it can also be used to identify places where different variants of the assembler require different syntax.

In the simplest case, a `%' followed by a digit n says to output operand n at that point in the string.

`%' followed by a letter and a digit says to output an operand in an alternate fashion. Four letters have standard, built-in meanings described below. The machine description macro PRINT_OPERAND can define additional letters with nonstandard meanings.

`%cdigit' can be used to substitute an operand that is a constant value without the syntax that normally indicates an immediate operand.

`%ndigit' is like `%cdigit' except that the value of the constant is negated before printing.

`%adigit' can be used to substitute an operand as if it were a memory reference, with the actual operand treated as the address. This may be useful when outputting a "load address" instruction, because often the assembler syntax for such an instruction requires you to write the operand as if it were a memory reference.

`%ldigit' is used to substitute a label_ref into a jump instruction.

`%=' outputs a number which is unique to each instruction in the entire compilation. This is useful for making local labels to be referred to more than once in a single template that generates multiple assembler instructions.

`%' followed by a punctuation character specifies a substitution that does not use an operand. Only one case is standard: `%%' outputs a `%' into the assembler code. Other nonstandard cases can be defined in the PRINT_OPERAND macro. You must also define which punctuation characters are valid with the PRINT_OPERAND_PUNCT_VALID_P macro.

The template may generate multiple assembler instructions. Write the text for the instructions, with `\;' between them.

When the RTL contains two operands which are required by constraint to match each other, the output template must refer only to the lower-numbered operand. Matching operands are not always identical, and the rest of the compiler arranges to put the proper RTL expression for printing into the lower-numbered operand.

One use of nonstandard letters or punctuation following `%' is to distinguish between different assembler languages for the same machine; for example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax requires periods in most opcode names, while MIT syntax does not. For example, the opcode `movel' in MIT syntax is `move.l' in Motorola syntax. The same file of patterns is used for both kinds of output syntax, but the character sequence `%.' is used in each place where Motorola syntax wants a period. The PRINT_OPERAND macro for Motorola syntax defines the sequence to output a period; the macro for MIT syntax defines it to do nothing.

As a special case, a template consisting of the single character # instructs the compiler to first split the insn, and then output the resulting instructions separately. This helps eliminate redundancy in the output templates. If you have a define_insn that needs to emit multiple assembler instructions, and there is an matching define_split already defined, then you can simply use # as the output template instead of writing an output template that emits the multiple assembler instructions.

If the macro ASSEMBLER_DIALECT is defined, you can use construct of the form `{option0|option1|option2}' in the templates. These describe multiple variants of assembler language syntax. See section 21.17.7 Output of Assembler Instructions.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.6 C Statements for Assembler Output

Often a single fixed template string cannot produce correct and efficient assembler code for all the cases that are recognized by a single instruction pattern. For example, the opcodes may depend on the kinds of operands; or some unfortunate combinations of operands may require extra machine instructions.

If the output control string starts with a `@', then it is actually a series of templates, each on a separate line. (Blank lines and leading spaces and tabs are ignored.) The templates correspond to the pattern's constraint alternatives (see section 20.7.2 Multiple Alternative Constraints). For example, if a target machine has a two-address add instruction `addr' to add into a register and another `addm' to add a register to memory, you might write this pattern:

(define_insn "addsi3"
  [(set (match_operand:SI 0 "general_operand" "=r,m")
        (plus:SI (match_operand:SI 1 "general_operand" "0,0")
                 (match_operand:SI 2 "general_operand" "g,r")))]
   addr %2,%0
   addm %2,%0")

If the output control string starts with a `*', then it is not an output template but rather a piece of C program that should compute a template. It should execute a return statement to return the template-string you want. Most such templates use C string literals, which require doublequote characters to delimit them. To include these doublequote characters in the string, prefix each one with `\'.

The operands may be found in the array operands, whose C data type is rtx [].

It is very common to select different ways of generating assembler code based on whether an immediate operand is within a certain range. Be careful when doing this, because the result of INTVAL is an integer on the host machine. If the host machine has more bits in an int than the target machine has in the mode in which the constant will be used, then some of the bits you get from INTVAL will be superfluous. For proper results, you must carefully disregard the values of those bits.

It is possible to output an assembler instruction and then go on to output or compute more of them, using the subroutine output_asm_insn. This receives two arguments: a template-string and a vector of operands. The vector may be operands, or it may be another array of rtx that you declare locally and initialize yourself.

When an insn pattern has multiple alternatives in its constraints, often the appearance of the assembler code is determined mostly by which alternative was matched. When this is so, the C code can test the variable which_alternative, which is the ordinal number of the alternative that was actually satisfied (0 for the first, 1 for the second alternative, etc.).

For example, suppose there are two opcodes for storing zero, `clrreg' for registers and `clrmem' for memory locations. Here is how a pattern could use which_alternative to choose between them:

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=r,m")
        (const_int 0))]
  return (which_alternative == 0
          ? \"clrreg %0\" : \"clrmem %0\");

The example above, where the assembler code to generate was solely determined by the alternative, could also have been specified as follows, having the output control string start with a `@':

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=r,m")
        (const_int 0))]
   clrreg %0
   clrmem %0")

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.7 Operand Constraints

Each match_operand in an instruction pattern can specify a constraint for the type of operands allowed. Constraints can say whether an operand may be in a register, and which kinds of register; whether the operand can be a memory reference, and which kinds of address; whether the operand may be an immediate constant, and which possible values it may have. Constraints can also require two operands to match.

20.7.1 Simple Constraints  Basic use of constraints.
20.7.2 Multiple Alternative Constraints  When an insn has two alternative constraint-patterns.
20.7.3 Register Class Preferences  Constraints guide which hard register to put things in.
20.7.4 Constraint Modifier Characters  More precise control over effects of constraints.
20.7.5 Constraints for Particular Machines  Existing constraints for some particular machines.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.7.1 Simple Constraints

The simplest kind of constraint is a string full of letters, each of which describes one kind of operand that is permitted. Here are the letters that are allowed:

Whitespace characters are ignored and can be inserted at any position except the first. This enables each alternative for different operands to be visually aligned in the machine description even if they have different number of constraints and modifiers.

A memory operand is allowed, with any kind of address that the machine supports in general.

A memory operand is allowed, but only if the address is offsettable. This means that adding a small integer (actually, the width in bytes of the operand, as determined by its machine mode) may be added to the address and the result is also a valid memory address.

For example, an address which is constant is offsettable; so is an address that is the sum of a register and a constant (as long as a slightly larger constant is also within the range of address-offsets supported by the machine); but an autoincrement or autodecrement address is not offsettable. More complicated indirect/indexed addresses may or may not be offsettable depending on the other addressing modes that the machine supports.

Note that in an output operand which can be matched by another operand, the constraint letter `o' is valid only when accompanied by both `<' (if the target machine has predecrement addressing) and `>' (if the target machine has preincrement addressing).

A memory operand that is not offsettable. In other words, anything that would fit the `m' constraint but not the `o' constraint.

A memory operand with autodecrement addressing (either predecrement or postdecrement) is allowed.

A memory operand with autoincrement addressing (either preincrement or postincrement) is allowed.

A register operand is allowed provided that it is in a general register.

An immediate integer operand (one with constant value) is allowed. This includes symbolic constants whose values will be known only at assembly time.

An immediate integer operand with a known numeric value is allowed. Many systems cannot support assembly-time constants for operands less than a word wide. Constraints for these operands should use `n' rather than `i'.

`I', `J', `K', ... `P'
Other letters in the range `I' through `P' may be defined in a machine-dependent fashion to permit immediate integer operands with explicit integer values in specified ranges. For example, on the 68000, `I' is defined to stand for the range of values 1 to 8. This is the range permitted as a shift count in the shift instructions.

An immediate floating operand (expression code const_double) is allowed, but only if the target floating point format is the same as that of the host machine (on which the compiler is running).

An immediate floating operand (expression code const_double) is allowed.

`G', `H'
`G' and `H' may be defined in a machine-dependent fashion to permit immediate floating operands in particular ranges of values.

An immediate integer operand whose value is not an explicit integer is allowed.

This might appear strange; if an insn allows a constant operand with a value not known at compile time, it certainly must allow any known value. So why use `s' instead of `i'? Sometimes it allows better code to be generated.

For example, on the 68000 in a fullword instruction it is possible to use an immediate operand; but if the immediate value is between -128 and 127, better code results from loading the value into a register and using the register. This is because the load into the register can be done with a `moveq' instruction. We arrange for this to happen by defining the letter `K' to mean "any integer outside the range -128 to 127", and then specifying `Ks' in the operand constraints.

Any register, memory or immediate integer operand is allowed, except for registers that are not general registers.

Any operand whatsoever is allowed, even if it does not satisfy general_operand. This is normally used in the constraint of a match_scratch when certain alternatives will not actually require a scratch register.

`0', `1', `2', ... `9'
An operand that matches the specified operand number is allowed. If a digit is used together with letters within the same alternative, the digit should come last.

This is called a matching constraint and what it really means is that the assembler has only a single operand that fills two roles considered separate in the RTL insn. For example, an add insn has two input operands and one output operand in the RTL, but on most CISC machines an add instruction really has only two operands, one of them an input-output operand:

addl #35,r12

Matching constraints are used in these circumstances. More precisely, the two operands that match must include one input-only operand and one output-only operand. Moreover, the digit must be a smaller number than the number of the operand that uses it in the constraint.

For operands to match in a particular case usually means that they are identical-looking RTL expressions. But in a few special cases specific kinds of dissimilarity are allowed. For example, *x as an input operand will match *x++ as an output operand. For proper results in such cases, the output template should always use the output-operand's number when printing the operand.

An operand that is a valid memory address is allowed. This is for "load address" and "push address" instructions.

`p' in the constraint must be accompanied by address_operand as the predicate in the match_operand. This predicate interprets the mode specified in the match_operand as the mode of the memory reference for which the address would be valid.

Other letters can be defined in machine-dependent fashion to stand for particular classes of registers or other arbitrary operand types. `d', `a' and `f' are defined on the 68000/68020 to stand for data, address and floating point registers.

The machine description macro REG_CLASS_FROM_LETTER has first cut at the otherwise unused letters. If it evaluates to NO_REGS, then EXTRA_CONSTRAINT is evaluated.

A typical use for EXTRA_CONSTRANT would be to distinguish certain types of memory references that affect other insn operands.

In order to have valid assembler code, each operand must satisfy its constraint. But a failure to do so does not prevent the pattern from applying to an insn. Instead, it directs the compiler to modify the code so that the constraint will be satisfied. Usually this is done by copying an operand into a register.

Contrast, therefore, the two instruction patterns that follow:

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=r")
        (plus:SI (match_dup 0)
                 (match_operand:SI 1 "general_operand" "r")))]

which has two operands, one of which must appear in two places, and

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=r")
        (plus:SI (match_operand:SI 1 "general_operand" "0")
                 (match_operand:SI 2 "general_operand" "r")))]

which has three operands, two of which are required by a constraint to be identical. If we are considering an insn of the form

(insn n prev next
  (set (reg:SI 3)
       (plus:SI (reg:SI 6) (reg:SI 109)))

the first pattern would not apply at all, because this insn does not contain two identical subexpressions in the right place. The pattern would say, "That does not look like an add instruction; try other patterns." The second pattern would say, "Yes, that's an add instruction, but there is something wrong with it." It would direct the reload pass of the compiler to generate additional insns to make the constraint true. The results might look like this:

(insn n2 prev n
  (set (reg:SI 3) (reg:SI 6))

(insn n n2 next
  (set (reg:SI 3)
       (plus:SI (reg:SI 3) (reg:SI 109)))

It is up to you to make sure that each operand, in each pattern, has constraints that can handle any RTL expression that could be present for that operand. (When multiple alternatives are in use, each pattern must, for each possible combination of operand expressions, have at least one alternative which can handle that combination of operands.) The constraints don't need to allow any possible operand--when this is the case, they do not constrain--but they must at least point the way to reloading any possible operand so that it will fit.

If the operand's predicate can recognize registers, but the constraint does not permit them, it can make the compiler crash. When this operand happens to be a register, the reload pass will be stymied, because it does not know how to copy a register temporarily into memory.

If the predicate accepts a unary operator, the constraint applies to the operand. For example, the MIPS processor at ISA level 3 supports an instruction which adds two registers in SImode to produce a DImode result, but only if the registers are correctly sign extended. This predicate for the input operands accepts a sign_extend of an SImode register. Write the constraint to indicate the type of register that is required for the operand of the sign_extend.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.7.2 Multiple Alternative Constraints

Sometimes a single instruction has multiple alternative sets of possible operands. For example, on the 68000, a logical-or instruction can combine register or an immediate value into memory, or it can combine any kind of operand into a register; but it cannot combine one memory location into another.

These constraints are represented as multiple alternatives. An alternative can be described by a series of letters for each operand. The overall constraint for an operand is made from the letters for this operand from the first alternative, a comma, the letters for this operand from the second alternative, a comma, and so on until the last alternative. Here is how it is done for fullword logical-or on the 68000:

(define_insn "iorsi3"
  [(set (match_operand:SI 0 "general_operand" "=m,d")
        (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
                (match_operand:SI 2 "general_operand" "dKs,dmKs")))]

The first alternative has `m' (memory) for operand 0, `0' for operand 1 (meaning it must match operand 0), and `dKs' for operand 2. The second alternative has `d' (data register) for operand 0, `0' for operand 1, and `dmKs' for operand 2. The `=' and `%' in the constraints apply to all the alternatives; their meaning is explained in the next section (see section 20.7.3 Register Class Preferences).

If all the operands fit any one alternative, the instruction is valid. Otherwise, for each alternative, the compiler counts how many instructions must be added to copy the operands so that that alternative applies. The alternative requiring the least copying is chosen. If two alternatives need the same amount of copying, the one that comes first is chosen. These choices can be altered with the `?' and `!' characters:

Disparage slightly the alternative that the `?' appears in, as a choice when no alternative applies exactly. The compiler regards this alternative as one unit more costly for each `?' that appears in it.

Disparage severely the alternative that the `!' appears in. This alternative can still be used if it fits without reloading, but if reloading is needed, some other alternative will be used.

When an insn pattern has multiple alternatives in its constraints, often the appearance of the assembler code is determined mostly by which alternative was matched. When this is so, the C code for writing the assembler code can use the variable which_alternative, which is the ordinal number of the alternative that was actually satisfied (0 for the first, 1 for the second alternative, etc.). See section 20.6 C Statements for Assembler Output.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.7.3 Register Class Preferences

The operand constraints have another function: they enable the compiler to decide which kind of hardware register a pseudo register is best allocated to. The compiler examines the constraints that apply to the insns that use the pseudo register, looking for the machine-dependent letters such as `d' and `a' that specify classes of registers. The pseudo register is put in whichever class gets the most "votes". The constraint letters `g' and `r' also vote: they vote in favor of a general register. The machine description says which registers are considered general.

Of course, on some machines all registers are equivalent, and no register classes are defined. Then none of this complexity is relevant.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.7.4 Constraint Modifier Characters

Here are constraint modifier characters.

Means that this operand is write-only for this instruction: the previous value is discarded and replaced by output data.

Means that this operand is both read and written by the instruction.

When the compiler fixes up the operands to satisfy the constraints, it needs to know which operands are inputs to the instruction and which are outputs from it. `=' identifies an output; `+' identifies an operand that is both input and output; all other operands are assumed to be input only.

If you specify `=' or `+' in a constraint, you put it in the first character of the constraint string.

Means (in a particular alternative) that this operand is an earlyclobber operand, which is modified before the instruction is finished using the input operands. Therefore, this operand may not lie in a register that is used as an input operand or as part of any memory address.

`&' applies only to the alternative in which it is written. In constraints with multiple alternatives, sometimes one alternative requires `&' while others do not. See, for example, the `movdf' insn of the 68000.

An input operand can be tied to an earlyclobber operand if its only use as an input occurs before the early result is written. Adding alternatives of this form often allows GCC to produce better code when only some of the inputs can be affected by the earlyclobber. See, for example, the `mulsi3' insn of the ARM.

`&' does not obviate the need to write `='.

Declares the instruction to be commutative for this operand and the following operand. This means that the compiler may interchange the two operands if that is the cheapest way to make all operands fit the constraints. This is often used in patterns for addition instructions that really have only two operands: the result must go in one of the arguments. Here for example, is how the 68000 halfword-add instruction is defined:

(define_insn "addhi3"
  [(set (match_operand:HI 0 "general_operand" "=m,r")
     (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
              (match_operand:HI 2 "general_operand" "di,g")))]

Says that all following characters, up to the next comma, are to be ignored as a constraint. They are significant only for choosing register preferences.

Says that the following character should be ignored when choosing register preferences. `*' has no effect on the meaning of the constraint as a constraint, and no effect on reloading.

Here is an example: the 68000 has an instruction to sign-extend a halfword in a data register, and can also sign-extend a value by copying it into an address register. While either kind of register is acceptable, the constraints on an address-register destination are less strict, so it is best if register allocation makes an address register its goal. Therefore, `*' is used so that the `d' constraint letter (for data register) is ignored when computing register preferences.

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "general_operand" "=*d,a")
         (match_operand:HI 1 "general_operand" "0,g")))]

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.7.5 Constraints for Particular Machines

Whenever possible, you should use the general-purpose constraint letters in asm arguments, since they will convey meaning more readily to people reading your code. Failing that, use the constraint letters that usually have very similar meanings across architectures. The most commonly used constraints are `m' and `r' (for memory and general-purpose registers respectively; see section 20.7.1 Simple Constraints), and `I', usually the letter indicating the most common immediate-constant format.

For each machine architecture, the `config/machine.h' file defines additional constraints. These constraints are used by the compiler itself for instruction generation, as well as for asm statements; therefore, some of the constraints are not particularly interesting for asm. The constraints are defined through these macros:

Register class constraints (usually lower case).

Immediate constant constraints, for non-floating point constants of word size or smaller precision (usually upper case).

Immediate constant constraints, for all floating point constants and for constants of greater than word size precision (usually upper case).

Special cases of registers or memory. This macro is not required, and is only defined for some machines.

Inspecting these macro definitions in the compiler source for your machine is the best way to be certain you have the right constraints. However, here is a summary of the machine-dependent constraints available on some particular machines.

ARM family---`arm.h'
Floating-point register

One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0 or 10.0

Floating-point constant that would satisfy the constraint `F' if it were negated

Integer that is valid as an immediate operand in a data processing instruction. That is, an integer in the range 0 to 255 rotated by a multiple of 2

Integer in the range -4095 to 4095

Integer that satisfies constraint `I' when inverted (ones complement)

Integer that satisfies constraint `I' when negated (twos complement)

Integer in the range 0 to 32

A memory reference where the exact address is in a single register (``m'' is preferable for asm statements)

An item in the constant pool

A symbol in the text segment of the current file

AMD 29000 family---`a29k.h'
Local register 0

Byte Pointer (`BP') register

`Q' register

Special purpose register

First accumulator register

Other accumulator register

Floating point register

Constant greater than 0, less than 0x100

Constant greater than 0, less than 0x10000

Constant whose high 24 bits are on (1)

16-bit constant whose high 8 bits are on (1)

32-bit constant whose high 16 bits are on (1)

32-bit negative constant that fits in 8 bits

The constant 0x80000000 or, on the 29050, any 32-bit constant whose low 16 bits are 0.

16-bit negative constant that fits in 8 bits

A floating point constant (in asm statements, use the machine independent `E' or `F' instead)

AVR family---`avr.h'
Registers from r0 to r15

Registers from r16 to r23

Registers from r16 to r31

Registers from r24 to r31. These registers can be used in `adiw' command

Pointer register (r26--r31)

Base pointer register (r28--r31)

Stack pointer register (SPH:SPL)

Temporary register r0

Register pair X (r27:r26)

Register pair Y (r29:r28)

Register pair Z (r31:r30)

Constant greater than -1, less than 64

Constant greater than -64, less than 1

Constant integer 2

Constant integer 0

Constant that fits in 8 bits

Constant integer -1

Constant integer 8, 16, or 24

Constant integer 1

A floating point constant 0.0

IBM RS6000---`rs6000.h'
Address base register

Floating point register

`MQ', `CTR', or `LINK' register

`MQ' register

`CTR' register

`LINK' register

`CR' register (condition register) number 0

`CR' register (condition register)

`FPMEM' stack memory for FPR-GPR transfers

Signed 16-bit constant

Unsigned 16-bit constant shifted left 16 bits (use `L' instead for SImode constants)

Unsigned 16-bit constant

Signed 16-bit constant shifted left 16 bits

Constant larger than 31

Exact power of 2


Constant whose negation is a signed 16-bit constant

Floating point constant that can be loaded into a register with one instruction per word

Memory operand that is an offset from a register (`m' is preferable for asm statements)

AIX TOC entry

Constant suitable as a 64-bit mask operand

Constant suitable as a 32-bit mask operand

System V Release 4 small data area reference

Intel 386---`i386.h'
`a', b, c, or d register

Specifies the `a' or `d' registers. This is primarily useful for 64-bit integer values intended to be returned with the `d' register holding the most significant bits and the `a' register holding the least significant bits.

Floating point register

First (top of stack) floating point register

Second floating point register

`a' register

`b' register

`c' register

`d' register

`di' register

`si' register

Constant in range 0 to 31 (for 32-bit shifts)

Constant in range 0 to 63 (for 64-bit shifts)



0, 1, 2, or 3 (shifts for lea instruction)

Constant in range 0 to 255 (for out instruction)

Standard 80387 floating point constant

Intel 960---`i960.h'
Floating point register (fp0 to fp3)

Local register (r0 to r15)

Global register (g0 to g15)

Any local or global register

Integers from 0 to 31


Integers from -31 to 0

Floating point 0

Floating point 1

General-purpose integer register

Floating-point register (if available)

`Hi' register

`Lo' register

`Hi' or `Lo' register

General-purpose integer register

Floating-point status register

Signed 16-bit constant (for arithmetic instructions)


Zero-extended 16-bit constant (for logic instructions)

Constant with low 16 bits zero (can be loaded with lui)

32-bit constant which requires two instructions to load (a constant which is not `I', `K', or `L')

Negative 16-bit constant

Exact power of two

Positive 16-bit constant

Floating point zero

Memory reference that can be loaded with more than one instruction (`m' is preferable for asm statements)

Memory reference that can be loaded with one instruction (`m' is preferable for asm statements)

Memory reference in external OSF/rose PIC format (`m' is preferable for asm statements)

Motorola 680x0---`m68k.h'
Address register

Data register

68881 floating-point register, if available

Sun FPA (floating-point) register, if available

First 16 Sun FPA registers, if available

Integer in the range 1 to 8

16-bit signed number

Signed number whose magnitude is greater than 0x80

Integer in the range -8 to -1

Signed number whose magnitude is greater than 0x100

Floating point constant that is not a 68881 constant

Floating point constant that can be used by Sun FPA

Motorola 68HC11 & 68HC12 families---`m68hc11.h'
Register 'a'

Register 'b'

Register 'd'

An 8-bit register

Temporary soft register _.tmp

A soft register _.d1 to _.d31

Stack pointer register

Register 'x'

Register 'y'

Pseudo register 'z' (replaced by 'x' or 'y' at the end)

An address register: x, y or z

An address register: x or y

Register pair (x:d) to form a 32-bit value

Constants in the range -65536 to 65535

Constants whose 16-bit low part is zero

Constant integer 1 or -1

Constant integer 16

Constants in the range -8 to 2

Floating-point register that can hold 32- or 64-bit values.

Floating-point register that can hold 64- or 128-bit values.

Signed 13-bit constant


32-bit constant with the low 12 bits clear (a constant that can be loaded with the sethi instruction)

Floating-point zero

Signed 13-bit constant, sign-extended to 32 or 64 bits

Floating-point constant whose integral representation can be moved into an integer register using a single sethi instruction

Floating-point constant whose integral representation can be moved into an integer register using a single mov instruction

Floating-point constant whose integral representation can be moved into an integer register using a high/lo_sum instruction sequence

Memory address aligned to an 8-byte boundary

Even register

Auxiliary (address) register (ar0-ar7)

Stack pointer register (sp)

Standard (32-bit) precision integer register

Extended (40-bit) precision register (r0-r11)

Block count register (bk)

Extended (40-bit) precision low register (r0-r7)

Extended (40-bit) precision register (r0-r1)

Extended (40-bit) precision register (r2-r3)

Repeat count register (rc)

Index register (ir0-ir1)

Status (condition code) register (st)

Data page register (dp)

Floating-point zero

Immediate 16-bit floating-point constant

Signed 16-bit constant

Signed 8-bit constant

Signed 5-bit constant

Unsigned 16-bit constant

Unsigned 8-bit constant

Ones complement of unsigned 16-bit constant

High 16-bit constant (32-bit constant with 16 LSBs zero)

Indirect memory reference with signed 8-bit or index register displacement

Indirect memory reference with unsigned 5-bit displacement

Indirect memory reference with 1 bit or index register displacement

Direct memory reference

Symbolic address

S/390 and zSeries---`s390.h'
Address register (general purpose register except r0)

Data register (arbitrary general purpose register)

Floating-point register

Unsigned 8-bit constant (0--255)

Unsigned 12-bit constant (0--4095)

Signed 16-bit constant (-32768--32767)

Unsigned 16-bit constant (0--65535)

Memory reference without index register

Symbolic constant suitable for use with the larl instruction

General-purpose 32-bit register

One-bit boolean register

MAC16 40-bit accumulator register

Signed 12-bit integer constant, for use in MOVI instructions

Signed 8-bit integer constant, for use in ADDI instructions

Integer constant valid for BccI instructions

Unsigned constant valid for BccUI instructions

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.8 Standard Pattern Names For Generation

Here is a table of the instruction names that are meaningful in the RTL generation pass of the compiler. Giving one of these names to an instruction pattern tells the RTL generation pass that it can use the pattern to accomplish a certain task.

Here m stands for a two-letter machine mode name, in lower case. This instruction pattern moves data with that machine mode from operand 1 to operand 0. For example, `movsi' moves full-word data.

If operand 0 is a subreg with mode m of a register whose own mode is wider than m, the effect of this instruction is to store the specified value in the part of the register that corresponds to mode m. The effect on the rest of the register is undefined.

This class of patterns is special in several ways. First of all, each of these names up to and including full word size must be defined, because there is no other way to copy a datum from one place to another. If there are patterns accepting operands in larger modes, `movm' must be defined for integer modes of those sizes.

Second, these patterns are not used solely in the RTL generation pass. Even the reload pass can generate move insns to copy values from stack slots into temporary registers. When it does so, one of the operands is a hard register and the other is an operand that can need to be reloaded into a register.

Therefore, when given such a pair of operands, the pattern must generate RTL which needs no reloading and needs no temporary registers--no registers other than the operands. For example, if you support the pattern with a define_expand, then in such a case the define_expand mustn't call force_reg or any other such function which might generate new pseudo registers.

This requirement exists even for subword modes on a RISC machine where fetching those modes from memory normally requires several insns and some temporary registers.

During reload a memory reference with an invalid address may be passed as an operand. Such an address will be replaced with a valid address later in the reload pass. In this case, nothing may be done with the address except to use it as it stands. If it is copied, it will not be replaced with a valid address. No attempt should be made to make such an address into a valid address and no routine (such as change_address) that will do so may be called. Note that general_operand will fail when applied to such an address.

The global variable reload_in_progress (which must be explicitly declared if required) can be used to determine whether such special handling is required.

The variety of operands that have reloads depends on the rest of the machine description, but typically on a RISC machine these can only be pseudo registers that did not get hard registers, while on other machines explicit memory references will get optional reloads.

If a scratch register is required to move an object to or from memory, it can be allocated using gen_reg_rtx prior to life analysis.

If there are cases needing scratch registers after reload, you must define SECONDARY_INPUT_RELOAD_CLASS and perhaps also SECONDARY_OUTPUT_RELOAD_CLASS to detect them, and provide patterns `reload_inm' or `reload_outm' to handle them. See section 21.7 Register Classes.

The global variable no_new_pseudos can be used to determine if it is unsafe to create new pseudo registers. If this variable is nonzero, then it is unsafe to call gen_reg_rtx to allocate a new pseudo.

The constraints on a `movm' must permit moving any hard register to any other hard register provided that HARD_REGNO_MODE_OK permits mode m in both registers and REGISTER_MOVE_COST applied to their classes returns a value of 2.

It is obligatory to support floating point `movm' instructions into and out of any registers that can hold fixed point values, because unions and structures (which have modes SImode or DImode) can be in those registers and they may have floating point members.

There may also be a need to support fixed point `movm' instructions in and out of floating point registers. Unfortunately, I have forgotten why this was so, and I don't know whether it is still true. If HARD_REGNO_MODE_OK rejects fixed point values in floating point registers, then the constraints of the fixed point `movm' instructions must be designed to avoid ever trying to reload into a floating point register.

Like `movm', but used when a scratch register is required to move between operand 0 and operand 1. Operand 2 describes the scratch register. See the discussion of the SECONDARY_RELOAD_CLASS macro in see section 21.7 Register Classes.

Like `movm' except that if operand 0 is a subreg with mode m of a register whose natural mode is wider, the `movstrictm' instruction is guaranteed not to alter any of the register except the part which belongs to mode m.

Load several consecutive memory locations into consecutive registers. Operand 0 is the first of the consecutive registers, operand 1 is the first memory location, and operand 2 is a constant: the number of consecutive registers.

Define this only if the target machine really has such an instruction; do not define this if the most efficient way of loading consecutive registers from memory is to do them one at a time.

On some machines, there are restrictions as to which consecutive registers can be stored into memory, such as particular starting or ending register numbers or only a range of valid counts. For those machines, use a define_expand (see section 20.14 Defining RTL Sequences for Code Generation) and make the pattern fail if the restrictions are not met.

Write the generated insn as a parallel with elements being a set of one register from the appropriate memory location (you may also need use or clobber elements). Use a match_parallel (see section 20.4 RTL Template) to recognize the insn. See `a29k.md' and `rs6000.md' for examples of the use of this insn pattern.

Similar to `load_multiple', but store several consecutive registers into consecutive memory locations. Operand 0 is the first of the consecutive memory locations, operand 1 is the first register, and operand 2 is a constant: the number of consecutive registers.

Add operand 2 and operand 1, storing the result in operand 0. All operands must have mode m. This can be used even on two-address machines, by means of constraints requiring operands 1 and 0 to be the same location.

`subm3', `mulm3'
`divm3', `udivm3', `modm3', `umodm3'
`sminm3', `smaxm3', `uminm3', `umaxm3'
`andm3', `iorm3', `xorm3'
Similar, for other arithmetic operations.

Multiply operands 1 and 2, which have mode HImode, and store a SImode product in operand 0.

`mulqihi3', `mulsidi3'
Similar widening-multiplication instructions of other widths.

`umulqihi3', `umulhisi3', `umulsidi3'
Similar widening-multiplication instructions that do unsigned multiplication.

Perform a signed multiplication of operands 1 and 2, which have mode m, and store the most significant half of the product in operand 0. The least significant half of the product is discarded.

Similar, but the multiplication is unsigned.

Signed division that produces both a quotient and a remainder. Operand 1 is divided by operand 2 to produce a quotient stored in operand 0 and a remainder stored in operand 3.

For machines with an instruction that produces both a quotient and a remainder, provide a pattern for `divmodm4' but do not provide patterns for `divm3' and `modm3'. This allows optimization in the relatively common case when both the quotient and remainder are computed.

If an instruction that just produces a quotient or just a remainder exists and is more efficient than the instruction that produces both, write the output routine of `divmodm4' to call find_reg_note and look for a REG_UNUSED note on the quotient or remainder and generate the appropriate instruction.

Similar, but does unsigned division.

Arithmetic-shift operand 1 left by a number of bits specified by operand 2, and store the result in operand 0. Here m is the mode of operand 0 and operand 1; operand 2's mode is specified by the instruction pattern, and the compiler will convert the operand to that mode before generating the instruction.

`ashrm3', `lshrm3', `rotlm3', `rotrm3'
Other shift and rotate instructions, analogous to the ashlm3 instructions.

Negate operand 1 and store the result in operand 0.

Store the absolute value of operand 1 into operand 0.

Store the square root of operand 1 into operand 0.

The sqrt built-in function of C always uses the mode which corresponds to the C data type double.

Store into operand 0 one plus the index of the least significant 1-bit of operand 1. If operand 1 is zero, store zero. m is the mode of operand 0; operand 1's mode is specified by the instruction pattern, and the compiler will convert the operand to that mode before generating the instruction.

The ffs built-in function of C always uses the mode which corresponds to the C data type int.

Store the bitwise-complement of operand 1 into operand 0.

Compare operand 0 and operand 1, and set the condition codes. The RTL pattern should look like this:

(set (cc0) (compare (match_operand:m 0 ...)
                    (match_operand:m 1 ...)))

Compare operand 0 against zero, and set the condition codes. The RTL pattern should look like this:

(set (cc0) (match_operand:m 0 ...))

`tstm' patterns should not be defined for machines that do not use (cc0). Doing so would confuse the optimizer since it would no longer be clear which set operations were comparisons. The `cmpm' patterns should be used instead.

Block move instruction. The addresses of the destination and source strings are the first two operands, and both are in mode Pmode.

The number of bytes to move is the third operand, in mode m. Usually, you specify word_mode for m. However, if you can generate better code knowing the range of valid lengths is smaller than those representable in a full word, you should provide a pattern with a mode corresponding to the range of values you can handle efficiently (e.g., QImode for values in the range 0--127; note we avoid numbers that appear negative) and also a pattern with word_mode.

The fourth operand is the known shared alignment of the source and destination, in the form of a const_int rtx. Thus, if the compiler knows that both source and destination are word-aligned, it may provide the value 4 for this operand.

Descriptions of multiple movstrm patterns can only be beneficial if the patterns for smaller modes have fewer restrictions on their first, second and fourth operands. Note that the mode m in movstrm does not impose any restriction on the mode of individually moved data units in the block.

These patterns need not give special consideration to the possibility that the source and destination strings might overlap.

Block clear instruction. The addresses of the destination string is the first operand, in mode Pmode. The number of bytes to clear is the second operand, in mode m. See `movstrm' for a discussion of the choice of mode.

The third operand is the known alignment of the destination, in the form of a const_int rtx. Thus, if the compiler knows that the destination is word-aligned, it may provide the value 4 for this operand.

The use for multiple clrstrm is as for movstrm.

Block compare instruction, with five operands. Operand 0 is the output; it has mode m. The remaining four operands are like the operands of `movstrm'. The two memory blocks specified are compared byte by byte in lexicographic order. The effect of the instruction is to store a value in operand 0 whose sign indicates the result of the comparison.

Compute the length of a string, with three operands. Operand 0 is the result (of mode m), operand 1 is a mem referring to the first character of the string, operand 2 is the character to search for (normally zero), and operand 3 is a constant describing the known alignment of the beginning of the string.

Convert signed integer operand 1 (valid for fixed point mode m) to floating point mode n and store in operand 0 (which has mode n).

Convert unsigned integer operand 1 (valid for fixed point mode m) to floating point mode n and store in operand 0 (which has mode n).

Convert operand 1 (valid for floating point mode m) to fixed point mode n as a signed number and store in operand 0 (which has mode n). This instruction's result is defined only when the value of operand 1 is an integer.

Convert operand 1 (valid for floating point mode m) to fixed point mode n as an unsigned number and store in operand 0 (which has mode n). This instruction's result is defined only when the value of operand 1 is an integer.

Convert operand 1 (valid for floating point mode m) to an integer value, still represented in floating point mode m, and store it in operand 0 (valid for floating point mode m).

Like `fixmn2' but works for any floating point value of mode m by converting the value to an integer.

Like `fixunsmn2' but works for any floating point value of mode m by converting the value to an integer.

Truncate operand 1 (valid for mode m) to mode n and store in operand 0 (which has mode n). Both modes must be fixed point or both floating point.

Sign-extend operand 1 (valid for mode m) to mode n and store in operand 0 (which has mode n). Both modes must be fixed point or both floating point.

Zero-extend operand 1 (valid for mode m) to mode n and store in operand 0 (which has mode n). Both modes must be fixed point.

Extract a bit-field from operand 1 (a register or memory operand), where operand 2 specifies the width in bits and operand 3 the starting bit, and store it in operand 0. Operand 0 must have mode word_mode. Operand 1 may have mode byte_mode or word_mode; often word_mode is allowed only for registers. Operands 2 and 3 must be valid for word_mode.

The RTL generation pass generates this instruction only with constants for operands 2 and 3.

The bit-field value is sign-extended to a full word integer before it is stored in operand 0.

Like `extv' except that the bit-field value is zero-extended.

Store operand 3 (which must be valid for word_mode) into a bit-field in operand 0, where operand 1 specifies the width in bits and operand 2 the starting bit. Operand 0 may have mode byte_mode or word_mode; often word_mode is allowed only for registers. Operands 1 and 2 must be valid for word_mode.

The RTL generation pass generates this instruction only with constants for operands 1 and 2.

Conditionally move operand 2 or operand 3 into operand 0 according to the comparison in operand 1. If the comparison is true, operand 2 is moved into operand 0, otherwise operand 3 is moved.

The mode of the operands being compared need not be the same as the operands being moved. Some machines, sparc64 for example, have instructions that conditionally move an integer value based on the floating point condition codes and vice versa.

If the machine does not have conditional move instructions, do not define these patterns.

Store zero or nonzero in the operand according to the condition codes. Value stored is nonzero iff the condition cond is true. cond is the name of a comparison operation expression code, such as eq, lt or leu.

You specify the mode that the operand must have when you write the match_operand expression. The compiler automatically sees which mode you have used and supplies an operand of that mode.

The value stored for a true condition must have 1 as its low bit, or else must be negative. Otherwise the instruction is not suitable and you should omit it from the machine description. You describe to the compiler exactly which value is stored by defining the macro STORE_FLAG_VALUE (see section 21.21 Miscellaneous Parameters). If a description cannot be found that can be used for all the `scond' patterns, you should omit those operations from the machine description.

These operations may fail, but should do so only in relatively uncommon cases; if they would fail for common cases involving integer comparisons, it is best to omit these patterns.

If these operations are omitted, the compiler will usually generate code that copies the constant one to the target and branches around an assignment of zero to the target. If this code is more efficient than the potential instructions used for the `scond' pattern followed by those required to convert the result into a 1 or a zero in SImode, you should omit the `scond' operations from the machine description.

Conditional branch instruction. Operand 0 is a label_ref that refers to the label to jump to. Jump if the condition codes meet condition cond.

Some machines do not follow the model assumed here where a comparison instruction is followed by a conditional branch instruction. In that case, the `cmpm' (and `tstm') patterns should simply store the operands away and generate all the required insns in a define_expand (see section 20.14 Defining RTL Sequences for Code Generation) for the conditional branch operations. All calls to expand `bcond' patterns are immediately preceded by calls to expand either a `cmpm' pattern or a `tstm' pattern.

Machines that use a pseudo register for the condition code value, or where the mode used for the comparison depends on the condition being tested, should also use the above mechanism. See section 20.11 Defining Jump Instruction Patterns.

The above discussion also applies to the `movmodecc' and `scond' patterns.

A jump inside a function; an unconditional branch. Operand 0 is the label_ref of the label to jump to. This pattern name is mandatory on all machines.

Subroutine call instruction returning no value. Operand 0 is the function to call; operand 1 is the number of bytes of arguments pushed as a const_int; operand 2 is the number of registers used as operands.

On most machines, operand 2 is not actually stored into the RTL pattern. It is supplied for the sake of some RISC machines which need to put this information into the assembler code; they can put it in the RTL instead of operand 1.

Operand 0 should be a mem RTX whose address is the address of the function. Note, however, that this address can be a symbol_ref expression even if it would not be a legitimate memory address on the target machine. If it is also not a valid argument for a call instruction, the pattern for this operation should be a define_expand (see section 20.14 Defining RTL Sequences for Code Generation) that places the address into a register and uses that register in the call instruction.

Subroutine call instruction returning a value. Operand 0 is the hard register in which the value is returned. There are three more operands, the same as the three operands of the `call' instruction (but with numbers increased by one).

Subroutines that return BLKmode objects use the `call' insn.

`call_pop', `call_value_pop'
Similar to `call' and `call_value', except used if defined and if RETURN_POPS_ARGS is nonzero. They should emit a parallel that contains both the function call and a set to indicate the adjustment made to the frame pointer.

For machines where RETURN_POPS_ARGS can be nonzero, the use of these patterns increases the number of functions for which the frame pointer can be eliminated, if desired.

Subroutine call instruction returning a value of any type. Operand 0 is the function to call; operand 1 is a memory location where the result of calling the function is to be stored; operand 2 is a parallel expression where each element is a set expression that indicates the saving of a function return value into the result block.

This instruction pattern should be defined to support __builtin_apply on machines where special instructions are needed to call a subroutine with arbitrary arguments or to save the value returned. This instruction pattern is required on machines that have multiple registers that can hold a return value (i.e. FUNCTION_VALUE_REGNO_P is true for more than one register).

Subroutine return instruction. This instruction pattern name should be defined only if a single instruction can do all the work of returning from a function.

Like the `movm' patterns, this pattern is also used after the RTL generation phase. In this case it is to support machines where multiple instructions are usually needed to return from a function, but some class of functions only requires one instruction to implement a return. Normally, the applicable functions are those which do not need to save any registers or allocate stack space.

For such machines, the condition specified in this pattern should only be true when reload_completed is nonzero and the function's epilogue would only be a single instruction. For machines with register windows, the routine leaf_function_p may be used to determine if a register window push is required.

Machines that have conditional return instructions should define patterns such as

(define_insn ""
  [(set (pc)
        (if_then_else (match_operator
                         0 "comparison_operator"
                         [(cc0) (const_int 0)])

where condition would normally be the same condition specified on the named `return' pattern.

Untyped subroutine return instruction. This instruction pattern should be defined to support __builtin_return on machines where special instructions are needed to return a value of any type.

Operand 0 is a memory location where the result of calling a function with __builtin_apply is stored; operand 1 is a parallel expression where each element is a set expression that indicates the restoring of a function return value from the result block.

No-op instruction. This instruction pattern name should always be defined to output a no-op in assembler code. (const_int 0) will do as an RTL pattern.

An instruction to jump to an address which is operand zero. This pattern name is mandatory on all machines.

Instruction to jump through a dispatch table, including bounds checking. This instruction takes five operands:

  1. The index to dispatch on, which has mode SImode.

  2. The lower bound for indices in the table, an integer constant.

  3. The total range of indices in the table--the largest index minus the smallest one (both inclusive).

  4. A label that precedes the table itself.

  5. A label to jump to if the index has a value outside the bounds. (If the machine-description macro CASE_DROPS_THROUGH is defined, then an out-of-bounds index drops through to the code following the jump table instead of jumping to this label. In that case, this label is not actually used by the `casesi' instruction, but it is always provided as an operand.)

The table is a addr_vec or addr_diff_vec inside of a jump_insn. The number of elements in the table is one plus the difference between the upper bound and the lower bound.

Instruction to jump to a variable address. This is a low-level capability which can be used to implement a dispatch table when there is no `casesi' pattern.

This pattern requires two operands: the address or offset, and a label which should immediately precede the jump table. If the macro CASE_VECTOR_PC_RELATIVE evaluates to a nonzero value then the first operand is an offset which counts from the address of the table; otherwise, it is an absolute address to jump to. In either case, the first operand has mode Pmode.

The `tablejump' insn is always the last insn before the jump table it uses. Its assembler code normally has no need to use the second operand, but you should incorporate it in the RTL pattern so that the jump optimizer will not delete the table as unreachable code.

Conditional branch instruction that decrements a register and jumps if the register is nonzero. Operand 0 is the register to decrement and test; operand 1 is the label to jump to if the register is nonzero. See section 20.12 Defining Looping Instruction Patterns.

This optional instruction pattern is only used by the combiner, typically for loops reversed by the loop optimizer when strength reduction is enabled.

Conditional branch instruction that decrements a register and jumps if the register is nonzero. This instruction takes five operands: Operand 0 is the register to decrement and test; operand 1 is the number of loop iterations as a const_int or const0_rtx if this cannot be determined until run-time; operand 2 is the actual or estimated maximum number of iterations as a const_int; operand 3 is the number of enclosed loops as a const_int (an innermost loop has a value of 1); operand 4 is the label to jump to if the register is nonzero. See section 20.12 Defining Looping Instruction Patterns.

This optional instruction pattern should be defined for machines with low-overhead looping instructions as the loop optimizer will try to modify suitable loops to utilize it. If nested low-overhead looping is not supported, use a define_expand (see section 20.14 Defining RTL Sequences for Code Generation) and make the pattern fail if operand 3 is not const1_rtx. Similarly, if the actual or estimated maximum number of iterations is too large for this instruction, make it fail.

Companion instruction to doloop_end required for machines that need to perform some initialisation, such as loading special registers used by a low-overhead looping instruction. If initialisation insns do not always need to be emitted, use a define_expand (see section 20.14 Defining RTL Sequences for Code Generation) and make it fail.

Canonicalize the function pointer in operand 1 and store the result into operand 0.

Operand 0 is always a reg and has mode Pmode; operand 1 may be a reg, mem, symbol_ref, const_int, etc and also has mode Pmode.

Canonicalization of a function pointer usually involves computing the address of the function which would be called if the function pointer were used in an indirect call.

Only define this pattern if function pointers on the target machine can have different values but still call the same function when used in an indirect call.

Most machines save and restore the stack pointer by copying it to or from an object of mode Pmode. Do not define these patterns on such machines.

Some machines require special handling for stack pointer saves and restores. On those machines, define the patterns corresponding to the non-standard cases by using a define_expand (see section 20.14 Defining RTL Sequences for Code Generation) that produces the required insns. The three types of saves and restores are:

  1. `save_stack_block' saves the stack pointer at the start of a block that allocates a variable-sized object, and `restore_stack_block' restores the stack pointer when the block is exited.

  2. `save_stack_function' and `restore_stack_function' do a similar job for the outermost block of a function and are used when the function allocates variable-sized objects or calls alloca. Only the epilogue uses the restored stack pointer, allowing a simpler save or restore sequence on some machines.

  3. `save_stack_nonlocal' is used in functions that contain labels branched to by nested functions. It saves the stack pointer in such a way that the inner function can use `restore_stack_nonlocal' to restore the stack pointer. The compiler generates code to restore the frame and argument pointer registers, but some machines require saving and restoring additional data such as register window information or stack backchains. Place insns in these patterns to save and restore any such required data.

When saving the stack pointer, operand 0 is the save area and operand 1 is the stack pointer. The mode used to allocate the save area defaults to Pmode but you can override that choice by defining the STACK_SAVEAREA_MODE macro (see section 21.4 Storage Layout). You must specify an integral mode, or VOIDmode if no save area is needed for a particular type of save (either because no save is needed or because a machine-specific save area can be used). Operand 0 is the stack pointer and operand 1 is the save area for restore operations. If `save_stack_block' is defined, operand 0 must not be VOIDmode since these saves can be arbitrarily nested.

A save area is a mem that is at a constant offset from virtual_stack_vars_rtx when the stack pointer is saved for use by nonlocal gotos and a reg in the other two cases.

Subtract (or add if STACK_GROWS_DOWNWARD is undefined) operand 1 from the stack pointer to create space for dynamically allocated data.

Store the resultant pointer to this space into operand 0. If you are allocating space from the main stack, do this by emitting a move insn to copy virtual_stack_dynamic_rtx to operand 0. If you are allocating the space elsewhere, generate code to copy the location of the space to operand 0. In the latter case, you must ensure this space gets freed when the corresponding space on the main stack is free.

Do not define this pattern if all that must be done is the subtraction. Some machines require other operations such as stack probes or maintaining the back chain. Define this pattern to emit those operations in addition to updating the stack pointer.

Some machines require instructions to be executed after space is allocated from the stack, for example to generate a reference at the bottom of the stack.

If you need to emit instructions before the stack has been adjusted, put them into the `allocate_stack' pattern. Otherwise, define this pattern to emit the required instructions.

No operands are provided.

If stack checking cannot be done on your system by probing the stack with a load or store instruction (see section 21.8.2 Specifying How Stack Checking is Done), define this pattern to perform the needed check and signaling an error if the stack has overflowed. The single operand is the location in the stack furthest from the current stack pointer that you need to validate. Normally, on machines where this pattern is needed, you would obtain the stack limit from a global or thread-specific variable or register.

Emit code to generate a non-local goto, e.g., a jump from one function to a label in an outer function. This pattern has four arguments, each representing a value to be used in the jump. The first argument is to be loaded into the frame pointer, the second is the address to branch to (code to dispatch to the actual label), the third is the address of a location where the stack is saved, and the last is the address of the label, to be placed in the location for the incoming static chain.

On most machines you need not define this pattern, since GCC will already generate the correct code, which is to load the frame pointer and static chain, restore the stack (using the `restore_stack_nonlocal' pattern, if defined), and jump indirectly to the dispatcher. You need only define this pattern if this code will not work on your machine.

This pattern, if defined, contains code needed at the target of a nonlocal goto after the code already generated by GCC. You will not normally need to define this pattern. A typical reason why you might need this pattern is if some value, such as a pointer to a global table, must be restored when the frame pointer is restored. Note that a nonlocal goto only occurs within a unit-of-translation, so a global table pointer that is shared by all functions of a given module need not be restored. There are no arguments.

This pattern, if defined, contains code needed at the site of an exception handler that isn't needed at the site of a nonlocal goto. You will not normally need to define this pattern. A typical reason why you might need this pattern is if some value, such as a pointer to a global table, must be restored after control flow is branched to the handler of an exception. There are no arguments.

This pattern, if defined, contains additional code needed to initialize the jmp_buf. You will not normally need to define this pattern. A typical reason why you might need this pattern is if some value, such as a pointer to a global table, must be restored. Though it is preferred that the pointer value be recalculated if possible (given the address of a label for instance). The single argument is a pointer to the jmp_buf. Note that the buffer is five words long and that the first three are normally used by the generic mechanism.

This pattern, if defined, contains code needed at the site of an built-in setjmp that isn't needed at the site of a nonlocal goto. You will not normally need to define this pattern. A typical reason why you might need this pattern is if some value, such as a pointer to a global table, must be restored. It takes one argument, which is the label to which builtin_longjmp transfered control; this pattern may be emitted at a small offset from that label.

This pattern, if defined, performs the entire action of the longjmp. You will not normally need to define this pattern unless you also define builtin_setjmp_setup. The single argument is a pointer to the jmp_buf.

This pattern, if defined, affects the way __builtin_eh_return, and thence the call frame exception handling library routines, are built. It is intended to handle non-trivial actions needed along the abnormal return path.

The pattern takes two arguments. The first is an offset to be applied to the stack pointer. It will have been copied to some appropriate location (typically EH_RETURN_STACKADJ_RTX) which will survive until after reload to when the normal epilogue is generated. The second argument is the address of the exception handler to which the function should return. This will normally need to copied by the pattern to some special register or memory location.

This pattern only needs to be defined if call frame exception handling is to be used, and simple moves to EH_RETURN_STACKADJ_RTX and EH_RETURN_HANDLER_RTX are not sufficient.

This pattern, if defined, emits RTL for entry to a function. The function entry is responsible for setting up the stack frame, initializing the frame pointer register, saving callee saved registers, etc.

Using a prologue pattern is generally preferred over defining FUNCTION_PROLOGUE to emit assembly code for the prologue.

The prologue pattern is particularly useful for targets which perform instruction scheduling.

This pattern, if defined, emits RTL for exit from a function. The function exit is responsible for deallocating the stack frame, restoring callee saved registers and emitting the return instruction.

Using an epilogue pattern is generally preferred over defining FUNCTION_EPILOGUE to emit assembly code for the prologue.

The epilogue pattern is particularly useful for targets which perform instruction scheduling or which have delay slots for their return instruction.

This pattern, if defined, emits RTL for exit from a function without the final branch back to the calling function. This pattern will be emitted before any sibling call (aka tail call) sites.

The sibcall_epilogue pattern must not clobber any arguments used for parameter passing or any stack slots for arguments passed to the current function.

This pattern, if defined, signals an error, typically by causing some kind of signal to be raised. Among other places, it is used by the Java front end to signal `invalid array index' exceptions.

Conditional trap instruction. Operand 0 is a piece of RTL which performs a comparison. Operand 1 is the trap code, an integer.

A typical conditional_trap pattern looks like

(define_insn "conditional_trap"
  [(trap_if (match_operator 0 "trap_operator"
             [(cc0) (const_int 0)])
            (match_operand 1 "const_int_operand" "i"))]


This pattern, if present, will be emitted by the instruction scheduler at the beginning of each new clock cycle. This can be used for annotating the assembler output with cycle counts. Operand 0 is a const_int that holds the clock cycle.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.9 When the Order of Patterns Matters

Sometimes an insn can match more than one instruction pattern. Then the pattern that appears first in the machine description is the one used. Therefore, more specific patterns (patterns that will match fewer things) and faster instructions (those that will produce better code when they do match) should usually go first in the description.

In some cases the effect of ordering the patterns can be used to hide a pattern when it is not valid. For example, the 68000 has an instruction for converting a fullword to floating point and another for converting a byte to floating point. An instruction converting an integer to floating point could match either one. We put the pattern to convert the fullword first to make sure that one will be used rather than the other. (Otherwise a large integer might be generated as a single-byte immediate quantity, which would not work.) Instead of using this pattern ordering it would be possible to make the pattern for convert-a-byte smart enough to deal properly with any constant value.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.10 Interdependence of Patterns

Every machine description must have a named pattern for each of the conditional branch names `bcond'. The recognition template must always have the form

(set (pc)
     (if_then_else (cond (cc0) (const_int 0))
                   (label_ref (match_operand 0 "" ""))

In addition, every machine description must have an anonymous pattern for each of the possible reverse-conditional branches. Their templates look like

(set (pc)
     (if_then_else (cond (cc0) (const_int 0))
                   (label_ref (match_operand 0 "" ""))))

They are necessary because jump optimization can turn direct-conditional branches into reverse-conditional branches.

It is often convenient to use the match_operator construct to reduce the number of patterns that must be specified for branches. For example,

(define_insn ""
  [(set (pc)
        (if_then_else (match_operator 0 "comparison_operator"
                                      [(cc0) (const_int 0)])
                      (label_ref (match_operand 1 "" ""))))]

In some cases machines support instructions identical except for the machine mode of one or more operands. For example, there may be "sign-extend halfword" and "sign-extend byte" instructions whose patterns are

(set (match_operand:SI 0 ...)
     (extend:SI (match_operand:HI 1 ...)))

(set (match_operand:SI 0 ...)
     (extend:SI (match_operand:QI 1 ...)))

Constant integers do not specify a machine mode, so an instruction to extend a constant value could match either pattern. The pattern it actually will match is the one that appears first in the file. For correct results, this must be the one for the widest possible mode (HImode, here). If the pattern matches the QImode instruction, the results will be incorrect if the constant value does not actually fit that mode.

Such instructions to extend constants are rarely generated because they are optimized away, but they do occasionally happen in nonoptimized compilations.

If a constraint in a pattern allows a constant, the reload pass may replace a register with a constant permitted by the constraint in some cases. Similarly for memory references. Because of this substitution, you should not provide separate patterns for increment and decrement instructions. Instead, they should be generated from the same pattern that supports register-register add insns by examining the operands and generating the appropriate machine instruction.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.11 Defining Jump Instruction Patterns

For most machines, GCC assumes that the machine has a condition code. A comparison insn sets the condition code, recording the results of both signed and unsigned comparison of the given operands. A separate branch insn tests the condition code and branches or not according its value. The branch insns come in distinct signed and unsigned flavors. Many common machines, such as the Vax, the 68000 and the 32000, work this way.

Some machines have distinct signed and unsigned compare instructions, and only one set of conditional branch instructions. The easiest way to handle these machines is to treat them just like the others until the final stage where assembly code is written. At this time, when outputting code for the compare instruction, peek ahead at the following branch using next_cc0_user (insn). (The variable insn refers to the insn being output, in the output-writing code in an instruction pattern.) If the RTL says that is an unsigned branch, output an unsigned compare; otherwise output a signed compare. When the branch itself is output, you can treat signed and unsigned branches identically.

The reason you can do this is that GCC always generates a pair of consecutive RTL insns, possibly separated by note insns, one to set the condition code and one to test it, and keeps the pair inviolate until the end.

To go with this technique, you must define the machine-description macro NOTICE_UPDATE_CC to do CC_STATUS_INIT; in other words, no compare instruction is superfluous.

Some machines have compare-and-branch instructions and no condition code. A similar technique works for them. When it is time to "output" a compare instruction, record its operands in two static variables. When outputting the branch-on-condition-code instruction that follows, actually output a compare-and-branch instruction that uses the remembered operands.

It also works to define patterns for compare-and-branch instructions. In optimizing compilation, the pair of compare and branch instructions will be combined according to these patterns. But this does not happen if optimization is not requested. So you must use one of the solutions above in addition to any special patterns you define.

In many RISC machines, most instructions do not affect the condition code and there may not even be a separate condition code register. On these machines, the restriction that the definition and use of the condition code be adjacent insns is not necessary and can prevent important optimizations. For example, on the IBM RS/6000, there is a delay for taken branches unless the condition code register is set three instructions earlier than the conditional branch. The instruction scheduler cannot perform this optimization if it is not permitted to separate the definition and use of the condition code register.

On these machines, do not use (cc0), but instead use a register to represent the condition code. If there is a specific condition code register in the machine, use a hard register. If the condition code or comparison result can be placed in any general register, or if there are multiple condition registers, use a pseudo register.

On some machines, the type of branch instruction generated may depend on the way the condition code was produced; for example, on the 68k and Sparc, setting the condition code directly from an add or subtract instruction does not clear the overflow bit the way that a test instruction does, so a different branch instruction must be used for some conditional branches. For machines that use (cc0), the set and use of the condition code must be adjacent (separated only by note insns) allowing flags in cc_status to be used. (See section 21.13 Condition Code Status.) Also, the comparison and branch insns can be located from each other by using the functions prev_cc0_setter and next_cc0_user.

However, this is not true on machines that do not use (cc0). On those machines, no assumptions can be made about the adjacency of the compare and branch insns and the above methods cannot be used. Instead, we use the machine mode of the condition code register to record different formats of the condition code register.

Registers used to store the condition code value should have a mode that is in class MODE_CC. Normally, it will be CCmode. If additional modes are required (as for the add example mentioned above in the Sparc), define the macro EXTRA_CC_MODES to list the additional modes required (see section 21.13 Condition Code Status). Also define SELECT_CC_MODE to choose a mode given an operand of a compare.

If it is known during RTL generation that a different mode will be required (for example, if the machine has separate compare instructions for signed and unsigned quantities, like most IBM processors), they can be specified at that time.

If the cases that require different modes would be made by instruction combination, the macro SELECT_CC_MODE determines which machine mode should be used for the comparison result. The patterns should be written using that mode. To support the case of the add on the Sparc discussed above, we have the pattern

(define_insn ""
  [(set (reg:CC_NOOV 0)
          (plus:SI (match_operand:SI 0 "register_operand" "%r")
                   (match_operand:SI 1 "arith_operand" "rI"))
          (const_int 0)))]

The SELECT_CC_MODE macro on the Sparc returns CC_NOOVmode for comparisons whose argument is a plus.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.12 Defining Looping Instruction Patterns

Some machines have special jump instructions that can be utilised to make loops more efficient. A common example is the 68000 `dbra' instruction which performs a decrement of a register and a branch if the result was greater than zero. Other machines, in particular digital signal processors (DSPs), have special block repeat instructions to provide low-overhead loop support. For example, the TI TMS320C3x/C4x DSPs have a block repeat instruction that loads special registers to mark the top and end of a loop and to count the number of loop iterations. This avoids the need for fetching and executing a `dbra'-like instruction and avoids pipeline stalls associated with the jump.

GCC has three special named patterns to support low overhead looping, `decrement_and_branch_until_zero', `doloop_begin', and `doloop_end'. The first pattern, `decrement_and_branch_until_zero', is not emitted during RTL generation but may be emitted during the instruction combination phase. This requires the assistance of the loop optimizer, using information collected during strength reduction, to reverse a loop to count down to zero. Some targets also require the loop optimizer to add a REG_NONNEG note to indicate that the iteration count is always positive. This is needed if the target performs a signed loop termination test. For example, the 68000 uses a pattern similar to the following for its dbra instruction:

(define_insn "decrement_and_branch_until_zero"
  [(set (pc)
	  (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
		       (const_int -1))
	      (const_int 0))
	  (label_ref (match_operand 1 "" ""))
   (set (match_dup 0)
	(plus:SI (match_dup 0)
		 (const_int -1)))]
  "find_reg_note (insn, REG_NONNEG, 0)"

Note that since the insn is both a jump insn and has an output, it must deal with its own reloads, hence the `m' constraints. Also note that since this insn is generated by the instruction combination phase combining two sequential insns together into an implicit parallel insn, the iteration counter needs to be biased by the same amount as the decrement operation, in this case -1. Note that the following similar pattern will not be matched by the combiner.

(define_insn "decrement_and_branch_until_zero"
  [(set (pc)
	  (ge (match_operand:SI 0 "general_operand" "+d*am")
	      (const_int 1))
	  (label_ref (match_operand 1 "" ""))
   (set (match_dup 0)
	(plus:SI (match_dup 0)
		 (const_int -1)))]
  "find_reg_note (insn, REG_NONNEG, 0)"

The other two special looping patterns, `doloop_begin' and `doloop_end', are emitted by the loop optimiser for certain well-behaved loops with a finite number of loop iterations using information collected during strength reduction.

The `doloop_end' pattern describes the actual looping instruction (or the implicit looping operation) and the `doloop_begin' pattern is an optional companion pattern that can be used for initialisation needed for some low-overhead looping instructions.

Note that some machines require the actual looping instruction to be emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting the true RTL for a looping instruction at the top of the loop can cause problems with flow analysis. So instead, a dummy doloop insn is emitted at the end of the loop. The machine dependent reorg pass checks for the presence of this doloop insn and then searches back to the top of the loop, where it inserts the true looping insn (provided there are no instructions in the loop which would cause problems). Any additional labels can be emitted at this point. In addition, if the desired special iteration counter register was not allocated, this machine dependent reorg pass could emit a traditional compare and jump instruction pair.

The essential difference between the `decrement_and_branch_until_zero' and the `doloop_end' patterns is that the loop optimizer allocates an additional pseudo register for the latter as an iteration counter. This pseudo register cannot be used within the loop (i.e., general induction variables cannot be derived from it), however, in many cases the loop induction variable may become redundant and removed by the flow pass.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.13 Canonicalization of Instructions

There are often cases where multiple RTL expressions could represent an operation performed by a single machine instruction. This situation is most commonly encountered with logical, branch, and multiply-accumulate instructions. In such cases, the compiler attempts to convert these multiple RTL expressions into a single canonical form to reduce the number of insn patterns required.

In addition to algebraic simplifications, following canonicalizations are performed:

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.14 Defining RTL Sequences for Code Generation

On some target machines, some standard pattern names for RTL generation cannot be handled with single insn, but a sequence of RTL insns can represent them. For these target machines, you can write a define_expand to specify how to generate the sequence of RTL.

A define_expand is an RTL expression that looks almost like a define_insn; but, unlike the latter, a define_expand is used only for RTL generation and it can produce more than one RTL insn.

A define_expand RTX has four operands:

Every RTL insn emitted by a define_expand must match some define_insn in the machine description. Otherwise, the compiler will crash when trying to generate code for the insn or trying to optimize it.

The RTL template, in addition to controlling generation of RTL insns, also describes the operands that need to be specified when this pattern is used. In particular, it gives a predicate for each operand.

A true operand, which needs to be specified in order to generate RTL from the pattern, should be described with a match_operand in its first occurrence in the RTL template. This enters information on the operand's predicate into the tables that record such things. GCC uses the information to preload the operand into a register if that is required for valid RTL code. If the operand is referred to more than once, subsequent references should use match_dup.

The RTL template may also refer to internal "operands" which are temporary registers or labels used only within the sequence made by the define_expand. Internal operands are substituted into the RTL template with match_dup, never with match_operand. The values of the internal operands are not passed in as arguments by the compiler when it requests use of this pattern. Instead, they are computed within the pattern, in the preparation statements. These statements compute the values and store them into the appropriate elements of operands so that match_dup can find them.

There are two special macros defined for use in the preparation statements: DONE and FAIL. Use them with a following semicolon, as a statement.

Use the DONE macro to end RTL generation for the pattern. The only RTL insns resulting from the pattern on this occasion will be those already emitted by explicit calls to emit_insn within the preparation statements; the RTL template will not be generated.

Make the pattern fail on this occasion. When a pattern fails, it means that the pattern was not truly available. The calling routines in the compiler will try other strategies for code generation using other patterns.

Failure is currently supported only for binary (addition, multiplication, shifting, etc.) and bit-field (extv, extzv, and insv) operations.

If the preparation falls through (invokes neither DONE nor FAIL), then the define_expand acts like a define_insn in that the RTL template is used to generate the insn.

The RTL template is not used for matching, only for generating the initial insn list. If the preparation statement always invokes DONE or FAIL, the RTL template may be reduced to a simple list of operands, such as this example:

(define_expand "addsi3"
  [(match_operand:SI 0 "register_operand" "")
   (match_operand:SI 1 "register_operand" "")
   (match_operand:SI 2 "register_operand" "")]
  handle_add (operands[0], operands[1], operands[2]);

Here is an example, the definition of left-shift for the SPUR chip:

(define_expand "ashlsi3"
  [(set (match_operand:SI 0 "register_operand" "")
          (match_operand:SI 1 "register_operand" "")
          (match_operand:SI 2 "nonmemory_operand" "")))]

  if (GET_CODE (operands[2]) != CONST_INT
      || (unsigned) INTVAL (operands[2]) > 3)

This example uses define_expand so that it can generate an RTL insn for shifting when the shift-count is in the supported range of 0 to 3 but fail in other cases where machine insns aren't available. When it fails, the compiler tries another strategy using different patterns (such as, a library call).

If the compiler were able to handle nontrivial condition-strings in patterns with names, then it would be possible to use a define_insn in that case. Here is another case (zero-extension on the 68000) which makes more use of the power of define_expand:

(define_expand "zero_extendhisi2"
  [(set (match_operand:SI 0 "general_operand" "")
        (const_int 0))
   (set (strict_low_part
            (match_dup 0)
        (match_operand:HI 1 "general_operand" ""))]
  "operands[1] = make_safe_from (operands[1], operands[0]);")

Here two RTL insns are generated, one to clear the entire output operand and the other to copy the input operand into its low half. This sequence is incorrect if the input operand refers to [the old value of] the output operand, so the preparation statement makes sure this isn't so. The function make_safe_from copies the operands[1] into a temporary register if it refers to operands[0]. It does this by emitting another RTL insn.

Finally, a third example shows the use of an internal operand. Zero-extension on the SPUR chip is done by and-ing the result against a halfword mask. But this mask cannot be represented by a const_int because the constant value is too large to be legitimate on this machine. So it must be copied into a register with force_reg and then the register used in the and.

(define_expand "zero_extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "")
        (and:SI (subreg:SI
                  (match_operand:HI 1 "register_operand" "")
                (match_dup 2)))]
     = force_reg (SImode, GEN_INT (65535)); ")

Note: If the define_expand is used to serve a standard binary or unary arithmetic operation or a bit-field operation, then the last insn it generates must not be a code_label, barrier or note. It must be an insn, jump_insn or call_insn. If you don't need a real insn at the end, emit an insn to copy the result of the operation into itself. Such an insn will generate no code, but it can avoid problems in the compiler.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.15 Defining How to Split Instructions

There are two cases where you should specify how to split a pattern into multiple insns. On machines that have instructions requiring delay slots (see section 20.17.7 Delay Slot Scheduling) or that have instructions whose output is not available for multiple cycles (see section 20.17.8 Specifying Function Units), the compiler phases that optimize these cases need to be able to move insns into one-instruction delay slots. However, some insns may generate more than one machine instruction. These insns cannot be placed into a delay slot.

Often you can rewrite the single insn as a list of individual insns, each corresponding to one machine instruction. The disadvantage of doing so is that it will cause the compilation to be slower and require more space. If the resulting insns are too complex, it may also suppress some optimizations. The compiler splits the insn if there is a reason to believe that it might improve instruction or delay slot scheduling.

The insn combiner phase also splits putative insns. If three insns are merged into one insn with a complex expression that cannot be matched by some define_insn pattern, the combiner phase attempts to split the complex pattern into two insns that are recognized. Usually it can break the complex pattern into two patterns by splitting out some subexpression. However, in some other cases, such as performing an addition of a large constant in two insns on a RISC machine, the way to split the addition into two insns is machine-dependent.

The define_split definition tells the compiler how to split a complex insn into several simpler insns. It looks like this:


insn-pattern is a pattern that needs to be split and condition is the final condition to be tested, as in a define_insn. When an insn matching insn-pattern and satisfying condition is found, it is replaced in the insn list with the insns given by new-insn-pattern-1, new-insn-pattern-2, etc.

The preparation-statements are similar to those statements that are specified for define_expand (see section 20.14 Defining RTL Sequences for Code Generation) and are executed before the new RTL is generated to prepare for the generated code or emit some insns whose pattern is not fixed. Unlike those in define_expand, however, these statements must not generate any new pseudo-registers. Once reload has completed, they also must not allocate any space in the stack frame.

Patterns are matched against insn-pattern in two different circumstances. If an insn needs to be split for delay slot scheduling or insn scheduling, the insn is already known to be valid, which means that it must have been matched by some define_insn and, if reload_completed is nonzero, is known to satisfy the constraints of that define_insn. In that case, the new insn patterns must also be insns that are matched by some define_insn and, if reload_completed is nonzero, must also satisfy the constraints of those definitions.

As an example of this usage of define_split, consider the following example from `a29k.md', which splits a sign_extend from HImode to SImode into a pair of shift insns:

  [(set (match_operand:SI 0 "gen_reg_operand" "")
        (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
  [(set (match_dup 0)
        (ashift:SI (match_dup 1)
                   (const_int 16)))
   (set (match_dup 0)
        (ashiftrt:SI (match_dup 0)
                     (const_int 16)))]
{ operands[1] = gen_lowpart (SImode, operands[1]); }")

When the combiner phase tries to split an insn pattern, it is always the case that the pattern is not matched by any define_insn. The combiner pass first tries to split a single set expression and then the same set expression inside a parallel, but followed by a clobber of a pseudo-reg to use as a scratch register. In these cases, the combiner expects exactly two new insn patterns to be generated. It will verify that these patterns match some define_insn definitions, so you need not do this test in the define_split (of course, there is no point in writing a define_split that will never produce insns that match).

Here is an example of this use of define_split, taken from `rs6000.md':

  [(set (match_operand:SI 0 "gen_reg_operand" "")
        (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
                 (match_operand:SI 2 "non_add_cint_operand" "")))]
  [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
  int low = INTVAL (operands[2]) & 0xffff;
  int high = (unsigned) INTVAL (operands[2]) >> 16;

  if (low & 0x8000)
    high++, low |= 0xffff0000;

  operands[3] = GEN_INT (high << 16);
  operands[4] = GEN_INT (low);

Here the predicate non_add_cint_operand matches any const_int that is not a valid operand of a single add insn. The add with the smaller displacement is written so that it can be substituted into the address of a subsequent operation.

An example that uses a scratch register, from the same file, generates an equality comparison of a register and a large constant:

  [(set (match_operand:CC 0 "cc_reg_operand" "")
        (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
                    (match_operand:SI 2 "non_short_cint_operand" "")))
   (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
  "find_single_use (operands[0], insn, 0)
   && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
       || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
  [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
   (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
  /* Get the constant we are comparing against, C, and see what it
     looks like sign-extended to 16 bits.  Then see what constant
     could be XOR'ed with C to get the sign-extended value.  */

  int c = INTVAL (operands[2]);
  int sextc = (c << 16) >> 16;
  int xorv = c ^ sextc;

  operands[4] = GEN_INT (xorv);
  operands[5] = GEN_INT (sextc);

To avoid confusion, don't write a single define_split that accepts some insns that match some define_insn as well as some insns that don't. Instead, write two separate define_split definitions, one for the insns that are valid and one for the insns that are not valid.

For the common case where the pattern of a define_split exactly matches the pattern of a define_insn, use define_insn_and_split. It looks like this:


insn-pattern, condition, output-template, and insn-attributes are used as in define_insn. The new-insn-pattern vector and the preparation-statements are used as in a define_split. The split-condition is also used as in define_split, with the additional behavior that if the condition starts with `&&', the condition used for the split will be the constructed as a logical "and" of the split condition with the insn condition. For example, from i386.md:

(define_insn_and_split "zero_extendhisi2_and"
  [(set (match_operand:SI 0 "register_operand" "=r")
     (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
   (clobber (reg:CC 17))]
  "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
  "&& reload_completed"
  [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
	      (clobber (reg:CC 17))])]
  [(set_attr "type" "alu1")])

In this case, the actual split condition will be `TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed'.

The define_insn_and_split construction provides exactly the same functionality as two separate define_insn and define_split patterns. It exists for compactness, and as a maintenance tool to prevent having to ensure the two patterns' templates match.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.16 Machine-Specific Peephole Optimizers

In addition to instruction patterns the `md' file may contain definitions of machine-specific peephole optimizations.

The combiner does not notice certain peephole optimizations when the data flow in the program does not suggest that it should try them. For example, sometimes two consecutive insns related in purpose can be combined even though the second one does not appear to use a register computed in the first one. A machine-specific peephole optimizer can detect such opportunities.

There are two forms of peephole definitions that may be used. The original define_peephole is run at assembly output time to match insns and substitute assembly text. Use of define_peephole is deprecated.

A newer define_peephole2 matches insns and substitutes new insns. The peephole2 pass is run after register allocation but before scheduling, which may result in much better code for targets that do scheduling.

20.16.1 RTL to Text Peephole Optimizers  
20.16.2 RTL to RTL Peephole Optimizers  

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.16.1 RTL to Text Peephole Optimizers

A definition looks like this:


The last string operand may be omitted if you are not using any machine-specific information in this machine description. If present, it must obey the same rules as in a define_insn.

In this skeleton, insn-pattern-1 and so on are patterns to match consecutive insns. The optimization applies to a sequence of insns when insn-pattern-1 matches the first one, insn-pattern-2 matches the next, and so on.

Each of the insns matched by a peephole must also match a define_insn. Peepholes are checked only at the last stage just before code generation, and only optionally. Therefore, any insn which would match a peephole but no define_insn will cause a crash in code generation in an unoptimized compilation, or at various optimization stages.

The operands of the insns are matched with match_operands, match_operator, and match_dup, as usual. What is not usual is that the operand numbers apply to all the insn patterns in the definition. So, you can check for identical operands in two insns by using match_operand in one insn and match_dup in the other.

The operand constraints used in match_operand patterns do not have any direct effect on the applicability of the peephole, but they will be validated afterward, so make sure your constraints are general enough to apply whenever the peephole matches. If the peephole matches but the constraints are not satisfied, the compiler will crash.

It is safe to omit constraints in all the operands of the peephole; or you can write constraints which serve as a double-check on the criteria previously tested.

Once a sequence of insns matches the patterns, the condition is checked. This is a C expression which makes the final decision whether to perform the optimization (we do so if the expression is nonzero). If condition is omitted (in other words, the string is empty) then the optimization is applied to every sequence of insns that matches the patterns.

The defined peephole optimizations are applied after register allocation is complete. Therefore, the peephole definition can check which operands have ended up in which kinds of registers, just by looking at the operands.

The way to refer to the operands in condition is to write operands[i] for operand number i (as matched by (match_operand i ...)). Use the variable insn to refer to the last of the insns being matched; use prev_active_insn to find the preceding insns.

When optimizing computations with intermediate results, you can use condition to match only when the intermediate results are not used elsewhere. Use the C expression dead_or_set_p (insn, op), where insn is the insn in which you expect the value to be used for the last time (from the value of insn, together with use of prev_nonnote_insn), and op is the intermediate value (from operands[i]).

Applying the optimization means replacing the sequence of insns with one new insn. The template controls ultimate output of assembler code for this combined insn. It works exactly like the template of a define_insn. Operand numbers in this template are the same ones used in matching the original sequence of insns.

The result of a defined peephole optimizer does not need to match any of the insn patterns in the machine description; it does not even have an opportunity to match them. The peephole optimizer definition itself serves as the insn pattern to control how the insn is output.

Defined peephole optimizers are run as assembler code is being output, so the insns they produce are never combined or rearranged in any way.

Here is an example, taken from the 68000 machine description:

  [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
   (set (match_operand:DF 0 "register_operand" "=f")
        (match_operand:DF 1 "register_operand" "ad"))]
  "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
  rtx xoperands[2];
  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
  output_asm_insn (\"move.l %1,(sp)\", xoperands);
  output_asm_insn (\"move.l %1,-(sp)\", operands);
  return \"fmove.d (sp)+,%0\";
  output_asm_insn (\"movel %1,sp@\", xoperands);
  output_asm_insn (\"movel %1,sp@-\", operands);
  return \"fmoved sp@+,%0\";

The effect of this optimization is to change

jbsr _foobar
addql #4,sp
movel d1,sp@-
movel d0,sp@-
fmoved sp@+,fp0


jbsr _foobar
movel d1,sp@
movel d0,sp@-
fmoved sp@+,fp0

insn-pattern-1 and so on look almost like the second operand of define_insn. There is one important difference: the second operand of define_insn consists of one or more RTX's enclosed in square brackets. Usually, there is only one: then the same action can be written as an element of a define_peephole. But when there are multiple actions in a define_insn, they are implicitly enclosed in a parallel. Then you must explicitly write the parallel, and the square brackets within it, in the define_peephole. Thus, if an insn pattern looks like this,

(define_insn "divmodsi4"
  [(set (match_operand:SI 0 "general_operand" "=d")
        (div:SI (match_operand:SI 1 "general_operand" "0")
                (match_operand:SI 2 "general_operand" "dmsK")))
   (set (match_operand:SI 3 "general_operand" "=d")
        (mod:SI (match_dup 1) (match_dup 2)))]
  "divsl%.l %2,%3:%0")

then the way to mention this insn in a peephole is as follows:

    [(set (match_operand:SI 0 "general_operand" "=d")
          (div:SI (match_operand:SI 1 "general_operand" "0")
                  (match_operand:SI 2 "general_operand" "dmsK")))
     (set (match_operand:SI 3 "general_operand" "=d")
          (mod:SI (match_dup 1) (match_dup 2)))])

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.16.2 RTL to RTL Peephole Optimizers

The define_peephole2 definition tells the compiler how to substitute one sequence of instructions for another sequence, what additional scratch registers may be needed and what their lifetimes must be.


The definition is almost identical to define_split (see section 20.15 Defining How to Split Instructions) except that the pattern to match is not a single instruction, but a sequence of instructions.

It is possible to request additional scratch registers for use in the output template. If appropriate registers are not free, the pattern will simply not match.

Scratch registers are requested with a match_scratch pattern at the top level of the input pattern. The allocated register (initially) will be dead at the point requested within the original sequence. If the scratch is used at more than a single point, a match_dup pattern at the top level of the input pattern marks the last position in the input sequence at which the register must be available.

Here is an example from the IA-32 machine description:

  [(match_scratch:SI 2 "r")
   (parallel [(set (match_operand:SI 0 "register_operand" "")
                   (match_operator:SI 3 "arith_or_logical_operator"
                     [(match_dup 0)
                      (match_operand:SI 1 "memory_operand" "")]))
              (clobber (reg:CC 17))])]
  "! optimize_size && ! TARGET_READ_MODIFY"
  [(set (match_dup 2) (match_dup 1))
   (parallel [(set (match_dup 0)
                   (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
              (clobber (reg:CC 17))])]

This pattern tries to split a load from its use in the hopes that we'll be able to schedule around the memory load latency. It allocates a single SImode register of class GENERAL_REGS ("r") that needs to be live only at the point just before the arithmetic.

A real example requiring extended scratch lifetimes is harder to come by, so here's a silly made-up example:

  [(match_scratch:SI 4 "r")
   (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
   (set (match_operand:SI 2 "" "") (match_dup 1))
   (match_dup 4)
   (set (match_operand:SI 3 "" "") (match_dup 1))]
  "/* determine 1 does not overlap 0 and 2 */"
  [(set (match_dup 4) (match_dup 1))
   (set (match_dup 0) (match_dup 4))
   (set (match_dup 2) (match_dup 4))]
   (set (match_dup 3) (match_dup 4))]

If we had not added the (match_dup 4) in the middle of the input sequence, it might have been the case that the register we chose at the beginning of the sequence is killed by the first or second set.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.17 Instruction Attributes

In addition to describing the instruction supported by the target machine, the `md' file also defines a group of attributes and a set of values for each. Every generated insn is assigned a value for each attribute. One possible attribute would be the effect that the insn has on the machine's condition code. This attribute can then be used by NOTICE_UPDATE_CC to track the condition codes.

20.17.1 Defining Attributes and their Values  Specifying attributes and their values.
20.17.2 Attribute Expressions  Valid expressions for attribute values.
20.17.3 Assigning Attribute Values to Insns  Assigning attribute values to insns.
20.17.4 Example of Attribute Specifications  An example of assigning attributes.
20.17.5 Computing the Length of an Insn  Computing the length of insns.
20.17.6 Constant Attributes  Defining attributes that are constant.
20.17.7 Delay Slot Scheduling  Defining delay slots required for a machine.
20.17.8 Specifying Function Units  Specifying information for insn scheduling.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.17.1 Defining Attributes and their Values

The define_attr expression is used to define each attribute required by the target machine. It looks like:

(define_attr name list-of-values default)

name is a string specifying the name of the attribute being defined.

list-of-values is either a string that specifies a comma-separated list of values that can be assigned to the attribute, or a null string to indicate that the attribute takes numeric values.

default is an attribute expression that gives the value of this attribute for insns that match patterns whose definition does not include an explicit value for this attribute. See section 20.17.4 Example of Attribute Specifications, for more information on the handling of defaults. See section 20.17.6 Constant Attributes, for information on attributes that do not depend on any particular insn.

For each defined attribute, a number of definitions are written to the `insn-attr.h' file. For cases where an explicit set of values is specified for an attribute, the following are defined:

For example, if the following is present in the `md' file:

(define_attr "type" "branch,fp,load,store,arith" ...)

the following lines will be written to the file `insn-attr.h'.

#define HAVE_ATTR_type
enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
                 TYPE_STORE, TYPE_ARITH};
extern enum attr_type get_attr_type ();

If the attribute takes numeric values, no enum type will be defined and the function to obtain the attribute's value will return int.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.17.2 Attribute Expressions

RTL expressions used to define attributes use the codes described above plus a few specific to attribute definitions, to be discussed below. Attribute value expressions must have one of the following forms:

(const_int i)
The integer i specifies the value of a numeric attribute. i must be non-negative.

The value of a numeric attribute can be specified either with a const_int, or as an integer represented as a string in const_string, eq_attr (see below), attr, symbol_ref, simple arithmetic expressions, and set_attr overrides on specific instructions (see section 20.17.3 Assigning Attribute Values to Insns).

(const_string value)
The string value specifies a constant attribute value. If value is specified as `"*"', it means that the default value of the attribute is to be used for the insn containing this expression. `"*"' obviously cannot be used in the default expression of a define_attr.

If the attribute whose value is being specified is numeric, value must be a string containing a non-negative integer (normally const_int would be used in this case). Otherwise, it must contain one of the valid values for the attribute.

(if_then_else test true-value false-value)
test specifies an attribute test, whose format is defined below. The value of this expression is true-value if test is true, otherwise it is false-value.

(cond [test1 value1 ...] default)
The first operand of this expression is a vector containing an even number of expressions and consisting of pairs of test and value expressions. The value of the cond expression is that of the value corresponding to the first true test expression. If none of the test expressions are true, the value of the cond expression is that of the default expression.

test expressions can have one of the following forms:

(const_int i)
This test is true if i is nonzero and false otherwise.

(not test)
(ior test1 test2)
(and test1 test2)
These tests are true if the indicated logical function is true.

(match_operand:m n pred constraints)
This test is true if operand n of the insn whose attribute value is being determined has mode m (this part of the test is ignored if m is VOIDmode) and the function specified by the string pred returns a nonzero value when passed operand n and mode m (this part of the test is ignored if pred is the null string).

The constraints operand is ignored and should be the null string.

(le arith1 arith2)
(leu arith1 arith2)
(lt arith1 arith2)
(ltu arith1 arith2)
(gt arith1 arith2)
(gtu arith1 arith2)
(ge arith1 arith2)
(geu arith1 arith2)
(ne arith1 arith2)
(eq arith1 arith2)
These tests are true if the indicated comparison of the two arithmetic expressions is true. Arithmetic expressions are formed with plus, minus, mult, div, mod, abs, neg, and, ior, xor, not, ashift, lshiftrt, and ashiftrt expressions.

const_int and symbol_ref are always valid terms (see section 20.17.5 Computing the Length of an Insn,for additional forms). symbol_ref is a string denoting a C expression that yields an int when evaluated by the `get_attr_...' routine. It should normally be a global variable.

(eq_attr name value)
name is a string specifying the name of an attribute.

value is a string that is either a valid value for attribute name, a comma-separated list of values, or `!' followed by a value or list. If value does not begin with a `!', this test is true if the value of the name attribute of the current insn is in the list specified by value. If value begins with a `!', this test is true if the attribute's value is not in the specified list.

For example,

(eq_attr "type" "load,store")

is equivalent to

(ior (eq_attr "type" "load") (eq_attr "type" "store"))

If name specifies an attribute of `alternative', it refers to the value of the compiler variable which_alternative (see section 20.6 C Statements for Assembler Output) and the values must be small integers. For example,

(eq_attr "alternative" "2,3")

is equivalent to

(ior (eq (symbol_ref "which_alternative") (const_int 2))
     (eq (symbol_ref "which_alternative") (const_int 3)))

Note that, for most attributes, an eq_attr test is simplified in cases where the value of the attribute being tested is known for all insns matching a particular pattern. This is by far the most common case.

(attr_flag name)
The value of an attr_flag expression is true if the flag specified by name is true for the insn currently being scheduled.

name is a string specifying one of a fixed set of flags to test. Test the flags forward and backward to determine the direction of a conditional branch. Test the flags very_likely, likely, very_unlikely, and unlikely to determine if a conditional branch is expected to be taken.

If the very_likely flag is true, then the likely flag is also true. Likewise for the very_unlikely and unlikely flags.

This example describes a conditional branch delay slot which can be nullified for forward branches that are taken (annul-true) or for backward branches which are not taken (annul-false).

(define_delay (eq_attr "type" "cbranch")
  [(eq_attr "in_branch_delay" "true")
   (and (eq_attr "in_branch_delay" "true")
        (attr_flag "forward"))
   (and (eq_attr "in_branch_delay" "true")
        (attr_flag "backward"))])

The forward and backward flags are false if the current insn being scheduled is not a conditional branch.

The very_likely and likely flags are true if the insn being scheduled is not a conditional branch. The very_unlikely and unlikely flags are false if the insn being scheduled is not a conditional branch.

attr_flag is only used during delay slot scheduling and has no meaning to other passes of the compiler.

(attr name)
The value of another attribute is returned. This is most useful for numeric attributes, as eq_attr and attr_flag produce more efficient code for non-numeric attributes.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.17.3 Assigning Attribute Values to Insns

The value assigned to an attribute of an insn is primarily determined by which pattern is matched by that insn (or which define_peephole generated it). Every define_insn and define_peephole can have an optional last argument to specify the values of attributes for matching insns. The value of any attribute not specified in a particular insn is set to the default value for that attribute, as specified in its define_attr. Extensive use of default values for attributes permits the specification of the values for only one or two attributes in the definition of most insn patterns, as seen in the example in the next section.

The optional last argument of define_insn and define_peephole is a vector of expressions, each of which defines the value for a single attribute. The most general way of assigning an attribute's value is to use a set expression whose first operand is an attr expression giving the name of the attribute being set. The second operand of the set is an attribute expression (see section 20.17.2 Attribute Expressions) giving the value of the attribute.

When the attribute value depends on the `alternative' attribute (i.e., which is the applicable alternative in the constraint of the insn), the set_attr_alternative expression can be used. It allows the specification of a vector of attribute expressions, one for each alternative.

When the generality of arbitrary attribute expressions is not required, the simpler set_attr expression can be used, which allows specifying a string giving either a single attribute value or a list of attribute values, one for each alternative.

The form of each of the above specifications is shown below. In each case, name is a string specifying the attribute to be set.

(set_attr name value-string)
value-string is either a string giving the desired attribute value, or a string containing a comma-separated list giving the values for succeeding alternatives. The number of elements must match the number of alternatives in the constraint of the insn pattern.

Note that it may be useful to specify `*' for some alternative, in which case the attribute will assume its default value for insns matching that alternative.

(set_attr_alternative name [value1 value2 ...])
Depending on the alternative of the insn, the value will be one of the specified values. This is a shorthand for using a cond with tests on the `alternative' attribute.

(set (attr name) value)
The first operand of this set must be the special RTL expression attr, whose sole operand is a string giving the name of the attribute being set. value is the value of the attribute.

The following shows three different ways of representing the same attribute value specification:

(set_attr "type" "load,store,arith")

(set_attr_alternative "type"
                      [(const_string "load") (const_string "store")
                       (const_string "arith")])

(set (attr "type")
     (cond [(eq_attr "alternative" "1") (const_string "load")
            (eq_attr "alternative" "2") (const_string "store")]
           (const_string "arith")))

The define_asm_attributes expression provides a mechanism to specify the attributes assigned to insns produced from an asm statement. It has the form:

(define_asm_attributes [attr-sets])

where attr-sets is specified the same as for both the define_insn and the define_peephole expressions.

These values will typically be the "worst case" attribute values. For example, they might indicate that the condition code will be clobbered.

A specification for a length attribute is handled specially. The way to compute the length of an asm insn is to multiply the length specified in the expression define_asm_attributes by the number of machine instructions specified in the asm statement, determined by counting the number of semicolons and newlines in the string. Therefore, the value of the length attribute specified in a define_asm_attributes should be the maximum possible length of a single machine instruction.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.17.4 Example of Attribute Specifications

The judicious use of defaulting is important in the efficient use of insn attributes. Typically, insns are divided into types and an attribute, customarily called type, is used to represent this value. This attribute is normally used only to define the default value for other attributes. An example will clarify this usage.

Assume we have a RISC machine with a condition code and in which only full-word operations are performed in registers. Let us assume that we can divide all insns into loads, stores, (integer) arithmetic operations, floating point operations, and branches.

Here we will concern ourselves with determining the effect of an insn on the condition code and will limit ourselves to the following possible effects: The condition code can be set unpredictably (clobbered), not be changed, be set to agree with the results of the operation, or only changed if the item previously set into the condition code has been modified.

Here is part of a sample `md' file for such a machine:

(define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))

(define_attr "cc" "clobber,unchanged,set,change0"
             (cond [(eq_attr "type" "load")
                        (const_string "change0")
                    (eq_attr "type" "store,branch")
                        (const_string "unchanged")
                    (eq_attr "type" "arith")
                        (if_then_else (match_operand:SI 0 "" "")
                                      (const_string "set")
                                      (const_string "clobber"))]
                   (const_string "clobber")))

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=r,r,m")
        (match_operand:SI 1 "general_operand" "r,m,r"))]
   move %0,%1
   load %0,%1
   store %0,%1"
  [(set_attr "type" "arith,load,store")])

Note that we assume in the above example that arithmetic operations performed on quantities smaller than a machine word clobber the condition code since they will set the condition code to a value corresponding to the full-word result.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.17.5 Computing the Length of an Insn

For many machines, multiple types of branch instructions are provided, each for different length branch displacements. In most cases, the assembler will choose the correct instruction to use. However, when the assembler cannot do so, GCC can when a special attribute, the `length' attribute, is defined. This attribute must be defined to have numeric values by specifying a null string in its define_attr.

In the case of the `length' attribute, two additional forms of arithmetic terms are allowed in test expressions:

(match_dup n)
This refers to the address of operand n of the current insn, which must be a label_ref.

This refers to the address of the current insn. It might have been more consistent with other usage to make this the address of the next insn but this would be confusing because the length of the current insn is to be computed.

For normal insns, the length will be determined by value of the `length' attribute. In the case of addr_vec and addr_diff_vec insn patterns, the length is computed as the number of vectors multiplied by the size of each vector.

Lengths are measured in addressable storage units (bytes).

The following macros can be used to refine the length computation:

When the length insn attribute is used, this macro specifies the value to be assigned to the address of the first insn in a function. If not specified, 0 is used.

ADJUST_INSN_LENGTH (insn, length)
If defined, modifies the length assigned to instruction insn as a function of the context in which it is used. length is an lvalue that contains the initially computed length of the insn and should be updated with the correct length of the insn.

This macro will normally not be required. A case in which it is required is the ROMP. On this machine, the size of an addr_vec insn must be increased by two to compensate for the fact that alignment may be required.

The routine that returns get_attr_length (the value of the length attribute) can be used by the output routine to determine the form of the branch instruction to be written, as the example below illustrates.

As an example of the specification of variable-length branches, consider the IBM 360. If we adopt the convention that a register will be set to the starting address of a function, we can jump to labels within 4k of the start using a four-byte instruction. Otherwise, we need a six-byte sequence to load the address from memory and then branch to it.

On such a machine, a pattern for a branch instruction might be specified as follows:

(define_insn "jump"
  [(set (pc)
        (label_ref (match_operand 0 "" "")))]
   return (get_attr_length (insn) == 4
           ? \"b %l0\" : \"l r15,=a(%l0); br r15\");
  [(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096))
                                      (const_int 4)
                                      (const_int 6)))])

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.17.6 Constant Attributes

A special form of define_attr, where the expression for the default value is a const expression, indicates an attribute that is constant for a given run of the compiler. Constant attributes may be used to specify which variety of processor is used. For example,

(define_attr "cpu" "m88100,m88110,m88000"
  (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
         (symbol_ref "TARGET_88110") (const_string "m88110")]
        (const_string "m88000"))))

(define_attr "memory" "fast,slow"
  (if_then_else (symbol_ref "TARGET_FAST_MEM")
                (const_string "fast")
                (const_string "slow"))))

The routine generated for constant attributes has no parameters as it does not depend on any particular insn. RTL expressions used to define the value of a constant attribute may use the symbol_ref form, but may not use either the match_operand form or eq_attr forms involving insn attributes.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.17.7 Delay Slot Scheduling

The insn attribute mechanism can be used to specify the requirements for delay slots, if any, on a target machine. An instruction is said to require a delay slot if some instructions that are physically after the instruction are executed as if they were located before it. Classic examples are branch and call instructions, which often execute the following instruction before the branch or call is performed.

On some machines, conditional branch instructions can optionally annul instructions in the delay slot. This means that the instruction will not be executed for certain branch outcomes. Both instructions that annul if the branch is true and instructions that annul if the branch is false are supported.

Delay slot scheduling differs from instruction scheduling in that determining whether an instruction needs a delay slot is dependent only on the type of instruction being generated, not on data flow between the instructions. See the next section for a discussion of data-dependent instruction scheduling.

The requirement of an insn needing one or more delay slots is indicated via the define_delay expression. It has the following form:

(define_delay test
              [delay-1 annul-true-1 annul-false-1
               delay-2 annul-true-2 annul-false-2

test is an attribute test that indicates whether this define_delay applies to a particular insn. If so, the number of required delay slots is determined by the length of the vector specified as the second argument. An insn placed in delay slot n must satisfy attribute test delay-n. annul-true-n is an attribute test that specifies which insns may be annulled if the branch is true. Similarly, annul-false-n specifies which insns in the delay slot may be annulled if the branch is false. If annulling is not supported for that delay slot, (nil) should be coded.

For example, in the common case where branch and call insns require a single delay slot, which may contain any insn other than a branch or call, the following would be placed in the `md' file:

(define_delay (eq_attr "type" "branch,call")
              [(eq_attr "type" "!branch,call") (nil) (nil)])

Multiple define_delay expressions may be specified. In this case, each such expression specifies different delay slot requirements and there must be no insn for which tests in two define_delay expressions are both true.

For example, if we have a machine that requires one delay slot for branches but two for calls, no delay slot can contain a branch or call insn, and any valid insn in the delay slot for the branch can be annulled if the branch is true, we might represent this as follows:

(define_delay (eq_attr "type" "branch")
   [(eq_attr "type" "!branch,call")
    (eq_attr "type" "!branch,call")

(define_delay (eq_attr "type" "call")
              [(eq_attr "type" "!branch,call") (nil) (nil)
               (eq_attr "type" "!branch,call") (nil) (nil)])

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.17.8 Specifying Function Units

On most RISC machines, there are instructions whose results are not available for a specific number of cycles. Common cases are instructions that load data from memory. On many machines, a pipeline stall will result if the data is referenced too soon after the load instruction.

In addition, many newer microprocessors have multiple function units, usually one for integer and one for floating point, and often will incur pipeline stalls when a result that is needed is not yet ready.

The descriptions in this section allow the specification of how much time must elapse between the execution of an instruction and the time when its result is used. It also allows specification of when the execution of an instruction will delay execution of similar instructions due to function unit conflicts.

For the purposes of the specifications in this section, a machine is divided into function units, each of which execute a specific class of instructions in first-in-first-out order. Function units that accept one instruction each cycle and allow a result to be used in the succeeding instruction (usually via forwarding) need not be specified. Classic RISC microprocessors will normally have a single function unit, which we can call `memory'. The newer "superscalar" processors will often have function units for floating point operations, usually at least a floating point adder and multiplier.

Each usage of a function units by a class of insns is specified with a define_function_unit expression, which looks like this:

(define_function_unit name multiplicity simultaneity
                      test ready-delay issue-delay

name is a string giving the name of the function unit.

multiplicity is an integer specifying the number of identical units in the processor. If more than one unit is specified, they will be scheduled independently. Only truly independent units should be counted; a pipelined unit should be specified as a single unit. (The only common example of a machine that has multiple function units for a single instruction class that are truly independent and not pipelined are the two multiply and two increment units of the CDC 6600.)

simultaneity specifies the maximum number of insns that can be executing in each instance of the function unit simultaneously or zero if the unit is pipelined and has no limit.

All define_function_unit definitions referring to function unit name must have the same name and values for multiplicity and simultaneity.

test is an attribute test that selects the insns we are describing in this definition. Note that an insn may use more than one function unit and a function unit may be specified in more than one define_function_unit.

ready-delay is an integer that specifies the number of cycles after which the result of the instruction can be used without introducing any stalls.

issue-delay is an integer that specifies the number of cycles after the instruction matching the test expression begins using this unit until a subsequent instruction can begin. A cost of N indicates an N-1 cycle delay. A subsequent instruction may also be delayed if an earlier instruction has a longer ready-delay value. This blocking effect is computed using the simultaneity, ready-delay, issue-delay, and conflict-list terms. For a normal non-pipelined function unit, simultaneity is one, the unit is taken to block for the ready-delay cycles of the executing insn, and smaller values of issue-delay are ignored.

conflict-list is an optional list giving detailed conflict costs for this unit. If specified, it is a list of condition test expressions to be applied to insns chosen to execute in name following the particular insn matching test that is already executing in name. For each insn in the list, issue-delay specifies the conflict cost; for insns not in the list, the cost is zero. If not specified, conflict-list defaults to all instructions that use the function unit.

Typical uses of this vector are where a floating point function unit can pipeline either single- or double-precision operations, but not both, or where a memory unit can pipeline loads, but not stores, etc.

As an example, consider a classic RISC machine where the result of a load instruction is not available for two cycles (a single "delay" instruction is required) and where only one load instruction can be executed simultaneously. This would be specified as:

(define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)

For the case of a floating point function unit that can pipeline either single or double precision, but not both, the following could be specified:

   "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")])
   "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")])

Note: The scheduler attempts to avoid function unit conflicts and uses all the specifications in the define_function_unit expression. It has recently come to our attention that these specifications may not allow modeling of some of the newer "superscalar" processors that have insns using multiple pipelined units. These insns will cause a potential conflict for the second unit used during their execution and there is no way of representing that conflict. We welcome any examples of how function unit conflicts work in such processors and suggestions for their representation.

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.18 Conditional Execution

A number of architectures provide for some form of conditional execution, or predication. The hallmark of this feature is the ability to nullify most of the instructions in the instruction set. When the instruction set is large and not entirely symmetric, it can be quite tedious to describe these forms directly in the `.md' file. An alternative is the define_cond_exec template.


predicate-pattern is the condition that must be true for the insn to be executed at runtime and should match a relational operator. One can use match_operator to match several relational operators at once. Any match_operand operands must have no more than one alternative.

condition is a C expression that must be true for the generated pattern to match.

output-template is a string similar to the define_insn output template (see section 20.5 Output Templates and Operand Substitution), except that the `*' and `@' special cases do not apply. This is only useful if the assembly text for the predicate is a simple prefix to the main insn. In order to handle the general case, there is a global variable current_insn_predicate that will contain the entire predicate if the current insn is predicated, and will otherwise be NULL.

When define_cond_exec is used, an implicit reference to the predicable instruction attribute is made. See section 20.17 Instruction Attributes. This attribute must be boolean (i.e. have exactly two elements in its list-of-values). Further, it must not be used with complex expressions. That is, the default and all uses in the insns must be a simple constant, not dependent on the alternative or anything else.

For each define_insn for which the predicable attribute is true, a new define_insn pattern will be generated that matches a predicated version of the instruction. For example,

(define_insn "addsi"
  [(set (match_operand:SI 0 "register_operand" "r")
        (plus:SI (match_operand:SI 1 "register_operand" "r")
                 (match_operand:SI 2 "register_operand" "r")))]
  "add %2,%1,%0")

  [(ne (match_operand:CC 0 "register_operand" "c")
       (const_int 0))]

generates a new pattern

(define_insn ""
     (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
     (set (match_operand:SI 0 "register_operand" "r")
          (plus:SI (match_operand:SI 1 "register_operand" "r")
                   (match_operand:SI 2 "register_operand" "r"))))]
  "(test2) && (test1)"
  "(%3) add %2,%1,%0")

[ < ] [ > ]   [ << ] [ Up ] [ >> ]         [Top] [Contents] [Index] [ ? ]

20.19 Constant Definitions

Using literal constants inside instruction patterns reduces legibility and can be a maintenance problem.

To overcome this problem, you may use the define_constants expression. It contains a vector of name-value pairs. From that point on, wherever any of the names appears in the MD file, it is as if the corresponding value had been written instead. You may use define_constants multiple times; each appearance adds more constants to the table. It is an error to redefine a constant with a different value.

To come back to the a29k load multiple example, instead of

(define_insn ""
  [(match_parallel 0 "load_multiple_operation"
     [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
           (match_operand:SI 2 "memory_operand" "m"))
      (use (reg:SI 179))
      (clobber (reg:SI 179))])]
  "loadm 0,0,%1,%2")

You could write:

(define_constants [
    (R_BP 177)
    (R_FC 178)
    (R_CR 179)
    (R_Q  180)

(define_insn ""
  [(match_parallel 0 "load_multiple_operation"
     [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
           (match_operand:SI 2 "memory_operand" "m"))
      (use (reg:SI R_CR))
      (clobber (reg:SI R_CR))])]
  "loadm 0,0,%1,%2")

The constants that are defined with a define_constant are also output in the insn-codes.h header file as #defines.

[ << ] [ >> ]           [Top] [Contents] [Index] [ ? ]

This document was generated by GCC Administrator on February, 22 2002 using texi2html