This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
Re: Possible bug in cse.c affecting pre/post-modify mem access
On 05/10/2018 01:44 PM, A. Skrobov wrote:
> Hello,
>
> While working on a port of GCC for a non-public architecture that has
> pre/post-modify memory access instructions, I discovered what looks
> like a bug which can cause incorrect code generation.
>
> My suggested fix is trivial:
> https://github.com/tyomitch/gcc/commit/7d9cc102adf11065358d4694109ce3e9f0b5c642
> -- but I cannot submit this patch without a testcase, and my expertise
> in the standard GCC target architectures is insufficient for
> reproducing this bug in any one of them. So, perhaps a maintainer of
> any supported architecture having pre/post-modify memory access can
> take a look at this?
>
> Basically, it seems to me that if a BB has a sequence like (using C
> syntax for clarity)
>
> r1 = r2 + 42;
> r3 = *r1++;
> r4 = *(r2 + 42);
>
> --then the cse pass overlooks the modification of r1 by the second
> instruction, and changes the last instruction to "r4 = *r1"
My recollection is that auto-increment addressing modes should not
appear in the RTL in the CSE pass.
Where are the auto-increment addressing modes coming from?
jeff