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Re: Register allocation trouble

On 21/07/17 19:40, Nathan Sidwell wrote:
> On 07/21/2017 07:50 AM, Andrew Stubbs wrote:
>> (set (match_operand:SI "register_operand" "=a,b")
>>       (match_operand:SI "memory_operand"   "Ra,Rb"))
> How horrible would it be to split expose the entire mem:
> (set (match_operand:SI "register" "=a,b")
>      (mem:SI (match_operand:SI "register" "a,b")))
> + variants for reg+const if you have them?
> nathan

I have in the past pondered some form of MD rules for addressing modes:
something like

(define_mem_addr <name>
  (parallel [
    (match_operand:M 0 "register_operand" "constraint")
    (plus:M (match_operand:M 0 "register_operand" "constraint")
            (match_operand:M 1 "mem_offset_operand" "constraint"))
  [%0, %1]

such that you could express all the details of each addressing form.
You could then match these rules in your patterns and be explicit about
what was permitted in each case (including adding early-clobber
constraints -- really needed on ARM).  The parallel lists all the forms
permitted by this addressing rule.

It would be a lot of work however, and I've never pushed it beyond the
initial sketch above.  The hardest part is that this would involve
serious surgery in the register allocators.

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