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Supporting subreg style patterns


My hardware directly supports instructions of the form

    subreg:SI(reg:VEC v1,3) = SI:a1

That is, a particular field of a vector register can be used as the target of a move from a general register. Reginfo refuses to recognize that any registers can satisfy this subreg expression and therefore ira/reload/lra uses memory to make the transfer. If I allow vector registers to support SImode, I can get subreg 0 working, but no others since the various fields do not have a register equivalent. Are there any hooks or data structures to support this feature? Are there any examples in supported architectures?

Thanks

Shmeel



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