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(MIPS R5900) Adding support for the FPU (COP1) instructions
- From: Woon yung Liu <ysai187 at yahoo dot com>
- To: Gcc Mailing List <gcc at gcc dot gnu dot org>
- Date: Wed, 30 Mar 2016 09:26:20 +0000 (UTC)
- Subject: (MIPS R5900) Adding support for the FPU (COP1) instructions
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- Reply-to: Woon yung Liu <ysai187 at yahoo dot com>
Thank you all for the help so far. This is probably the final part of my efforts to complete support for the R5900 within GCC, but I need help this time because the existing homebrew GCC version has no support for this (despite what its README file says). Hence I have nothing to refer to.
The R5900 has support for a couple of floating-point arithmetic, with its FPU (COP1). The FPU instructions are something like these:
MADD.S (rd <- ACC + rs * rt)
MADDA.S (ACC <- ACC + rs * rt)
MSUB.S (rd <- ACC - rs * rt)
MSUBA.S (ACC <- ACC - rs * rt)
ADDA.S (ACC <- rs + rt)
SUBA.S (ACC <- rs - rt)
MULA.S (ACC <- rs * rt)
These instructions are similar to those floating-point instructions with similar-looking names, in normal MIPS processors. But they involve the R5900's FPU accumulator (ACC) register instead.
I didn't find an explicit instruction to move values to/from the ACC register.
I've added instruction patterns (or added new alternatives to existing patterns) to the pattern file for the R5900, but I have not seen GCC emit any of these new instructions. I did add a new register (the ACC register), as well as a matching constraint and predicate.
Is there a proper way for me to debug this? Or is this not working, simply because GCC can't support such instructions on its own (it looks complicated to issue)?
Thanks and regards,