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Re: Validity of SUBREG+AND-imm transformations
- From: Jeff Law <law at redhat dot com>
- To: Kyrill Tkachov <kyrylo dot tkachov at foss dot arm dot com>, Richard Biener <richard dot guenther at gmail dot com>, Segher Boessenkool <segher at kernel dot crashing dot org>
- Cc: "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>
- Date: Fri, 4 Mar 2016 22:52:44 -0700
- Subject: Re: Validity of SUBREG+AND-imm transformations
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On 03/04/2016 09:33 AM, Kyrill Tkachov wrote:
On 04/03/16 16:21, Jeff Law wrote:
On 03/04/2016 08:05 AM, Richard Biener wrote:
does that mean that the shift amount should be DImode?
Seems like a more flexible approach would be for the midend to be able
to handle these things...
Or macroize for all integer modes?
That's probably worth exploring. I wouldn't be at all surprised if it
that turns out to be better than any individual mode, not just for
arm & aarch64, but would help a variety of targets.
What do you mean by 'macroize' here? Do you mean use iterators to create
multple variants of patterns with different
modes on the shift amount?
I believe we'd still run into the issue at
We might, but I would expect the the number of incidences to be fewer.
Essentially we're giving the compiler multiple options when it comes to
representation of the shift amount -- allowing the compiler (combine in
particular) to use the shift amount in whatever mode is most natural.
ie, if the count is sitting in a QI, HI, SI or possibly even a DI
register, then it can be used as-is. No subregs, no zero/sign
extensions, or and-imm masking.