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Re: Instruction scheduling for the R5900's 2 integer pipelines

On 02/05/2016 05:35 AM, Woon yung Liu wrote:
The current (GCC 5.3.0) MIPS divmod<mode>4 pattern emits an expand
that allocates a temporary register (hi+lo) and emits other
instructions, depending if whether the target is a 32-bit or 64-bit
MIPS target.

However, it uses gen_rtx_REG to allocate the hi+lo register, while I
need it to freely allocate either one of the two (hi+lo or hi1+lo1)
that the r5900 has. With the current design, it will only use hi+lo
in all division ops (as with other MIPS).

I think that that I should be using gen_reg_rtx to allocate a pseudo
register, but that isn't possible in that expand (will result in an
assertion failure, due to can_create_pseudo_p).
Conditionalize the paths based on can_create_pseudo_p.

Essentially up until the register reloading pass you can freely create new pseudos. Once register reloading has begun, you can't create new pseudos. Though you might also look into why something would be calling the divmod expander after reload started -- that seems rather odd.


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