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Instruction scheduling for the R5900's 2 integer pipelines
- From: Woon yung Liu <ysai187 at yahoo dot com>
- To: "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>
- Date: Tue, 19 Jan 2016 12:04:16 +0000 (UTC)
- Subject: Instruction scheduling for the R5900's 2 integer pipelines
- Authentication-results: sourceware.org; auth=none
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- Reply-to: Woon yung Liu <ysai187 at yahoo dot com>
I'm am trying to complete support for the MIPS R5900, by adding support for its second
interger multiplication/division pipe. GCC currently supports only the first one.My target at this moment is the public GCC v5.3.0 release.
To get the 2nd pipeline supported, I've added the hi1 and lo1 registers to GCC, as well as
constraints for them (wr for hi1lo1 and wl for lo1). The existing instructions in mips.md have
been modified to use the new constraints as new alternatives.
A new constraint modifier was added too, which will append a 1 to the instruction (i.e.
changes mult to mult1) if it detects that the specified operand is for pipeline 1 instead of 0.
The 2nd pipeline is utilized by using different instructions (i.e. mult1 instead of mult, as
mult is for the 1st pipeline) and registers (i.e. lo1 and hi1, instead of lo and hi).
Right now, I know that it is possible for GCC to output the new instructions for the 2nd
pipeline if I manipulate the MD constrains for instructions like mult... but GCC doesn't seem
to be ever using the 2nd pipeline on its own otherwise.
I originally believed that it's because I didn't add in a pipeline description into my MD file
(5900.md), but nothing seemed to have changed after I did that.
I followed the documentation on the pipeline description, but I realized that I still don't
understand how the automatron will tell GCC which alternative (and hence which integer pipe)
to use and so I don't think think there's a relationship between the automatron and the two
different sets of multiplication/divisions instructions yet.
Could somebody please advice me on how to get this going? Or at least, tell me which other
target has two integer pipelines that are used in this way, so that I will have something to
AFAIK, no other MIPS processors have this 2nd pipeline design as the R5900.
Thanks and regards,