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[AArch64] A question about Cortex-A57 pipeline description
- From: Nikolai Bozhenov <n dot bozhenov at samsung dot com>
- To: "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>, james dot greenhalgh at arm dot com
- Date: Fri, 11 Sep 2015 18:31:37 +0300
- Subject: [AArch64] A question about Cortex-A57 pipeline description
- Authentication-results: sourceware.org; auth=none
Recently I got somewhat confused by Cortex-A57 pipeline description in
I would be grateful if you could help me understand a few unclear points.
Particularly I am interested in how memory operations (loads/stores) are
scheduled. It seems that according to the cortex-a57.md file, firstly, two
memory operations may never be scheduled at the same cycle and,
loads may never be scheduled at two consecutive cycles:
;; 5. Two pipelines for load and store operations: LS1, LS2. The most
;; valuable thing we can do is force a structural hazard to split
;; up loads/stores.
(define_cpu_unit "ca57_ls_issue" "cortex_a57")
(define_cpu_unit "ca57_ldr, ca57_str" "cortex_a57")
(define_reservation "ca57_load_model" "ca57_ls_issue,ca57_ldr*2")
(define_reservation "ca57_store_model" "ca57_ls_issue,ca57_str")
However, the Cortex-A57 Software Optimization Guide states that the core
to execute one load operation and one store operation every cycle. And that
agrees with my experiments. Indeed, a loop consisting of 10 loads, 10
several arithmetic operations takes on average about 10 cycles per
provided that the instructions are intermixed properly.
So, what is the purpose of additional restrictions imposed on the
cortex-a57.md file? It doesn't look like an error. Rather, it looks like a