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RE: Combined top-down and bottom-up instruction scheduler

> > Yes, that is true for OOO execution processors which can rearrange
> > insns and execute them speculatively looking through several branches.
> > For such processors, software pipelining is more important as the
> > processors can look only through a few branches as software pipelining
> > could look through any number of branches.  That is why Intel compiler
> > did not have any insn scheduler (but had software pipelining) until
> > Intel Atom introduction which was originally in-order processor.
> Correct.  Latency scheduling just isn't that important for OOO and instead
> you look at scheduling to mitigate costs for large latency operations (ie,
> cache miss  and transcendental functions).  You might also attack
> issues like throughput at the retirement stage for example.

Our motivation stems from the fact that even modern, aggressively OOO
processors don't have orthogonal resources.  Some insns depend on expensive
circuitry (area or power wise) that is added only once, making such insns
simply scalar, though most of other insns enjoy multiple resources capable
of executing them as superscalar.  That's why we believe that a hybrid
approach might yield good results.  We don't have data, for it possibly
requires implementing it first.

I'd also argue that looking at an OOO pipeline in a steady state is not the
only approach.  It's also important to consider how quickly the pipeline can
be replenished or warmed up to reach a steady state.

Evandro Menezes                              Austin, TX

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