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Re: [RFC] Combine related fail of gcc.target/powerpc/ti_math1.c


On Thu, May 21, 2015 at 11:34:14AM -0700, Richard Henderson wrote:
> On 05/21/2015 05:39 AM, Segher Boessenkool wrote:
> >> > Trying 18, 9 -> 24:
> >> > Failed to match this instruction:
> >> > (set (reg:DI 4 4 [+8 ])
> >> >     (plus:DI (plus:DI (reg:DI 5 5 [ val+8 ])
> >> >             (reg:DI 76 ca))
> >> >         (reg:DI 169 [+8 ])))
> > For some reason it has the CA reg not last.  I think we should add to
> > the canonicalisation rules so that fixed regs sort after other regs.
> > That requires a lot of testing.
> 
> Actually, I believe that the way CA is modeled at the moment is dangerous.
> It's not a 64-bit value, but a 1-bit value.

It's a fixed register and it is only ever set to 0 or 1.  There are
more targets that do such things, and it is safe.

I've tried with BImode before, with two effects: 1) the patterns become
much more unmanageable; and 2) the optimisers do a lousy job on it.
BImode isn't so well supported.

This was when I still modeled the carry output of "adde" and friends
though (it is always a clobber now).

> If we rearrange the expanded rtl to be (zero_extend:DI (reg:BI CA)), then
> normal canonicalization rules will apply and it'll always appear first in the
> chain of PLUS.

Let's wait for Alan's patch that makes combine not reorder things
unnecessarily, that should take care of it all as far as I see.


Segher


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