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Re: [RFC] Design for flag bit outputs from asms
- From: Linus Torvalds <torvalds at linux-foundation dot org>
- To: Richard Henderson <rth at redhat dot com>
- Cc: "H. Peter Anvin" <hpa at zytor dot com>, Peter Zijlstra <peterz at infradead dot org>, Vladimir Makarov <vmakarov at redhat dot com>, Jakub Jelinek <jakub at redhat dot com>, Ingo Molnar <mingo at kernel dot org>, Thomas Gleixner <tglx at linutronix dot de>, Linux Kernel Mailing List <linux-kernel at vger dot kernel dot org>, Borislav Petkov <bp at alien8 dot de>, "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>
- Date: Mon, 4 May 2015 13:45:06 -0700
- Subject: Re: [RFC] Design for flag bit outputs from asms
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On Mon, May 4, 2015 at 1:33 PM, Richard Henderson <email@example.com> wrote:
> A fair point. Though honestly, I was hoping that this feature would mostly be
> used for conditions that are "weird" -- that is, not normally describable by
> arithmetic at all. Otherwise, why are you using inline asm for it?
I could easily imagine using some of the combinations for atomic operations.
For example, doing a "lock decl", and wanting to see if the result is
negative or zero. Sure, it would be possible to set *two* booleans (ZF
and SF), but there's a contiional for "BE"..