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Re: [RFC] Design for flag bit outputs from asms
- From: Linus Torvalds <torvalds at linux-foundation dot org>
- To: "H. Peter Anvin" <hpa at zytor dot com>
- Cc: Richard Henderson <rth at redhat dot com>, Peter Zijlstra <peterz at infradead dot org>, Vladimir Makarov <vmakarov at redhat dot com>, Jakub Jelinek <jakub at redhat dot com>, Ingo Molnar <mingo at kernel dot org>, Thomas Gleixner <tglx at linutronix dot de>, Linux Kernel Mailing List <linux-kernel at vger dot kernel dot org>, Borislav Petkov <bp at alien8 dot de>, "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>
- Date: Mon, 4 May 2015 13:35:59 -0700
- Subject: Re: [RFC] Design for flag bit outputs from asms
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On Mon, May 4, 2015 at 1:14 PM, H. Peter Anvin <email@example.com> wrote:
> I would argue that for x86 what you actually want is to model the
> *conditions* that are available on the flags, not the flags themselves.
Yes. Otherwise it would be a nightmare to try to describe simple
conditions like "le", which a rather complicated combination of three
of the actual flag bits:
((SF ^^ OF) || ZF) = 1
which would just be ridiculously painful for (a) the user to describe
and (b) fior the compiler to recognize once described.
Now, I do admit that most of the cases where you'd use inline asm with
condition codes would probably fall into just simple "test ZF or CF".
But I could certainly imagine other cases.