This is the mail archive of the
mailing list for the GCC project.
Re: [i386] Scalar DImode instructions on XMM registers
- From: Ilya Enkovich <enkovich dot gnu at gmail dot com>
- To: Uros Bizjak <ubizjak at gmail dot com>
- Cc: GCC Development <gcc at gcc dot gnu dot org>
- Date: Fri, 24 Apr 2015 13:09:38 +0300
- Subject: Re: [i386] Scalar DImode instructions on XMM registers
- Authentication-results: sourceware.org; auth=none
- References: <CAMbmDYYT6zE86-xAYs08VV2nWDK6Np+qEYoj+6oGM276MtBuPQ at mail dot gmail dot com> <CAFULd4YVruAT=RHgENhBcuKZgE6FvRa=8aR6WygKm9F4GjnJyg at mail dot gmail dot com> <CAFULd4aycTg3bYKx7c9GXpgiY4WeqmLh1f5HFYL6K+K35QmTWA at mail dot gmail dot com>
2015-04-24 12:49 GMT+03:00 Uros Bizjak <email@example.com>:
> On Fri, Apr 24, 2015 at 11:45 AM, Uros Bizjak <firstname.lastname@example.org> wrote:
>> On Fri, Apr 24, 2015 at 11:22 AM, Ilya Enkovich <email@example.com> wrote:
>>> I was looking into PR65105 and tried to generate SSE computation for a
>>> simple 64bit a + b + c sequence. Having no scalar integer instructions in
>>> SSE I have to use vector variants.
>> Is this approach really better that having two add/addc instructions?
> FYI, V1DI mode was introduced because XMM shift insn were used to
> shift DImode values. The cost of moves from/to integer DImode reg pair
> was disastrous.
Does it mean I have to add V1DI instructions for all opcodes I want to
transform (add,sub,mul,or,and, etc.)?