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Re: Support for architectures without hardware interlocks
- From: Eric Botcazou <ebotcazou at adacore dot com>
- To: Claudiu Zissulescu <claziss at gmail dot com>
- Cc: gcc at gcc dot gnu dot org, Joel Sherrill <joel dot sherrill at oarcorp dot com>, David Kang <dkang at isi dot edu>
- Date: Thu, 08 Jan 2015 16:56:24 +0100
- Subject: Re: Support for architectures without hardware interlocks
- Authentication-results: sourceware.org; auth=none
- References: <1804367521 dot 968343 dot 1414782044572 dot JavaMail dot root at zm dot isi dot edu> <54AEA230 dot 1010307 at oarcorp dot com> <CAL0iMy3izTQesRbNuSBaBW9eD-vhebBJtJt9sagsNCxoxsWQ0g at mail dot gmail dot com>
> Handling the insertion of the nops at the end of RTL pipe needs to
> take also care of branch shortening optimizations, and filling delay
> slots. Probably for the given context (only FPU ops) may be a doable
> approach.
Right, you do it after delay slot filling and before branch shortening.
The new Visium port does that for all instructions (see visium_reorg).
--
Eric Botcazou