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Re: Instruction scheduler with respect to prefetch instructions.
- From: <Paul_Koning at Dell dot com>
- To: <ajit dot kumar dot agarwal at xilinx dot com>
- Cc: <vmakarov at redhat dot com>, <law at redhat dot com>, <richard dot guenther at gmail dot com>, <gcc at gcc dot gnu dot org>, <vinodk at xilinx dot com>, <shailadi at xilinx dot com>, <vidhum at xilinx dot com>, <nmekala at xilinx dot com>
- Date: Sat, 13 Dec 2014 16:15:49 +0000
- Subject: Re: Instruction scheduler with respect to prefetch instructions.
- Authentication-results: sourceware.org; auth=none
- References: <2f042c4a5035494baca0725a03c17276 at BN1AFFO11FD035 dot protection dot gbl>
> On Dec 13, 2014, at 5:22 AM, Ajit Kumar Agarwal <ajit.kumar.agarwal@xilinx.com> wrote:
>
> Hello All:
>
> Since the prefetch instruction have no direct consumers in the code stream, they provide considerable freedom to the
> Instruction scheduler. They are typically assigned lower priorities than most of the instructions in the code stream.
> This tends to cause all the prefetch instructions to be placed together in the final schedule. This causes the performance
> Degradations by placing them in clumps rather than evenly spreading the prefetch instructions.
>
> The evenly spreading the prefetch instruction gives better speed up ratios as compared to be placing in clumps for dirty
> Misses.
I can believe thatâs true for some processors; is it true for all of them? I have the impression that some MIPS processors donât mind clumped prefetches, so long as you donât exceed the limit on total number of concurrently pending memory accesses.
paul