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Instruction scheduler with respect to prefetch instructions.
- From: Ajit Kumar Agarwal <ajit dot kumar dot agarwal at xilinx dot com>
- To: Vladimir Makarov <vmakarov at redhat dot com>, Jeff Law <law at redhat dot com>, Richard Biener <richard dot guenther at gmail dot com>, "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>
- Cc: Vinod Kathail <vinodk at xilinx dot com>, Shail Aditya Gupta <shailadi at xilinx dot com>, Vidhumouli Hunsigida <vidhum at xilinx dot com>, "Nagaraju Mekala" <nmekala at xilinx dot com>
- Date: Sat, 13 Dec 2014 10:22:16 +0000
- Subject: Instruction scheduler with respect to prefetch instructions.
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Hello All:
Since the prefetch instruction have no direct consumers in the code stream, they provide considerable freedom to the
Instruction scheduler. They are typically assigned lower priorities than most of the instructions in the code stream.
This tends to cause all the prefetch instructions to be placed together in the final schedule. This causes the performance
Degradations by placing them in clumps rather than evenly spreading the prefetch instructions.
The evenly spreading the prefetch instruction gives better speed up ratios as compared to be placing in clumps for dirty
Misses.
I am curious to know how the schedulers in the GCC handles the prefetch instruction and how the priorities is assigned to
Prefetch instructions in the gcc schedulers so that the prefetch instruction is evenly spread.
Please let me know what do you think.
Thanks & Regards
Ajit