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Re: combination of read/write and earlyclobber constraint modifier
- From: Marc Glisse <marc dot glisse at inria dot fr>
- To: Tom de Vries <Tom_deVries at mentor dot com>
- Cc: gcc at gcc dot gnu dot org, Jeff Law <law at redhat dot com>, Vladimir Makarov <vmakarov at redhat dot com>
- Date: Wed, 2 Jul 2014 08:23:30 +0200 (CEST)
- Subject: Re: combination of read/write and earlyclobber constraint modifier
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- References: <53B30B96 dot 2000603 at mentor dot com> <53B31041 dot 8060608 at redhat dot com> <alpine dot DEB dot 2 dot 10 dot 1407012155000 dot 2640 at laptop-mg dot saclay dot inria dot fr> <53B32D3A dot 1030700 at mentor dot com>
- Reply-to: gcc at gcc dot gnu dot org
On Tue, 1 Jul 2014, Tom de Vries wrote:
On 01-07-14 21:58, Marc Glisse wrote:
So my question is: is the combination of '&' and '+' supported ? If so,
what is the exact semantics ? If not, should we warn or give an error ?
I don't think we can define any reasonable semantics for &+. My
recommendation would be for this to be considered a hard error.
Uh? The doc explicitly says "An input operand can be tied to an
operand" and goes on to explain why that is useful. It avoids using the
register for other input when they are identical.
That part of the doc refers to the mulsi3 insn for ARM as example:
;; Use `&' and then `0' to prevent the operands 0 and 1 being the same
[(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
(mult:SI (match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 1 "s_register_operand" "%0,r")))]
"TARGET_32BIT && !arm_arch6"
"mul%?\\t%0, %2, %1"
[(set_attr "type" "mul")
(set_attr "predicable" "yes")]
Note that there's no combination of & and + here.
I think it could have used (match_dup 0) instead of operand 1, if there
had been only the first alternative. And then the constraint would have
AFAIU, the 'tie' established here is from input operand 1 to an earlyclobber
output operand 0 using the '0' matching constraint.
Having said that, I don't understand the comment, AFAIU it should be: 'Use
'0' to make sure operands 0 and 1 are the same, and use '&' to make sure
operands 0 and 2 are not the same.
Well, yeah, the comment doesn't seem completely in sync with the code.
In the first example you gave, looking at the pattern (no match_dup,
setting the full register), it seems that it may have wanted "=&" instead
(by the way, in the same aarch64-simd.md file, I noticed some
define_expand with constraints, that looks strange)