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Re: combination of read/write and earlyclobber constraint modifier
- From: Tom de Vries <Tom_deVries at mentor dot com>
- To: <gcc at gcc dot gnu dot org>, Marc Glisse <marc dot glisse at inria dot fr>
- Cc: Jeff Law <law at redhat dot com>, Vladimir Makarov <vmakarov at redhat dot com>
- Date: Tue, 1 Jul 2014 23:50:50 +0200
- Subject: Re: combination of read/write and earlyclobber constraint modifier
- Authentication-results: sourceware.org; auth=none
- References: <53B30B96 dot 2000603 at mentor dot com> <53B31041 dot 8060608 at redhat dot com> <alpine dot DEB dot 2 dot 10 dot 1407012155000 dot 2640 at laptop-mg dot saclay dot inria dot fr>
On 01-07-14 21:58, Marc Glisse wrote:
So my question is: is the combination of '&' and '+' supported ? If so,
what is the exact semantics ? If not, should we warn or give an error ?
I don't think we can define any reasonable semantics for &+. My
recommendation would be for this to be considered a hard error.
Uh? The doc explicitly says "An input operand can be tied to an earlyclobber
operand" and goes on to explain why that is useful. It avoids using the same
register for other input when they are identical.
That part of the doc refers to the mulsi3 insn for ARM as example:
;; Use `&' and then `0' to prevent the operands 0 and 1 being the same
[(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
(mult:SI (match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 1 "s_register_operand" "%0,r")))]
"TARGET_32BIT && !arm_arch6"
"mul%?\\t%0, %2, %1"
[(set_attr "type" "mul")
(set_attr "predicable" "yes")]
Note that there's no combination of & and + here.
AFAIU, the 'tie' established here is from input operand 1 to an earlyclobber
output operand 0 using the '0' matching constraint.
Having said that, I don't understand the comment, AFAIU it should be: 'Use '0'
to make sure operands 0 and 1 are the same, and use '&' to make sure operands 0
and 2 are not the same.